Documentation Search in Resources Articles Manuals -OR- All Products Active-HDL Riviera-PRO ALINT-PRO HES-DVM HES Proto-AXI HES™ Boards RTAX/RTSX Adaptor Boards HES-DVM Proto Cloud Edition TySOM™ EDK DO-254/CTS All Documents Application Notes Manual Tutorial Videos FAQ Recorded Webinars Tutorials White Papers Technical Specification Case Studies All Categories Coverage 3rd Party Integration Design Entry, Documentation Simulation, Debugging Design Management, Libraries Advanced Verification Assertions and Functional Coverage RTL Simulation & Verification HDL Languages Encryption Military & Aerospace Verification Design Rule Checking Design Hardware Emulation Solutions Encryption Design HDL Languages RTL Simulation & Verification Assertions and Functional Coverage Advanced Verification Design Rule Checking Military & Aerospace Verification Hardware Emulation Solutions Tutorials Prototyping High-Level Synthesis Embedded Embedded Embedded High Performance Computer SoC & ASIC Prototyping Reset Results Name Products Type Action Enhancing VHDL Designs with Embedded PSL Abstract: PSL (Property Specification Language) is the easiest introduction to the world of design properties, assertions and coverage points to anybody familiar with VHDL (VHSIC Hardware Description Language). The designer of a digital circuit has the best understanding of the operation of the circuit, which makes her or him the best person to define properties that will fire assertion messages in case of incorrect design behavior during simulation or provide valuable feedback to the testbench creator by showing that all desired behaviors were covered during verification. For this reason, the use of embedded PSL properties and assertions is highly beneficial to the engineers and makes their designs better. Active-HDL White Papers Enhancing Verilog Designs with Embedded PSL Abstract: PSL (Property Specification Language) is one of the easiest introductions to the world of design properties, assertions and coverage points to anybody familiar with Verilog HDL. The designer of a digital circuit has the best understanding of the operation of the circuit, which makes her or him the best person to define properties that will fire assertion messages in case of incorrect design behavior during simulation or provide valuable feedback to the testbench creator by showing that all desired behaviors were covered during verification. For this reason, the use of embedded PSL properties and assertions is highly beneficial to the engineers and makes their designs better. Active-HDL White Papers Enhancing Verilog Designs with SVA Abstract: SVA (SystemVerilog Assertions) language is one of the easiest introductions to the world of design properties, assertions and coverage points to anybody familiar with Verilog HDL. The designer of a digital circuit has the best understanding of the operation of the circuit, which makes her or him the best person to define properties that will fire assertion messages in case of incorrect design behavior during simulation or provide valuable feedback to the testbench creator by showing that all desired behaviors were covered during verification. For this reason, the use of SVA properties and assertions directly in the design code is highly beneficial to the engineers and makes their designs better. Active-HDL White Papers Resets and Reset Domain Crossings in ASIC and FPGA designs This white paper explains Reset-related ASIC and FPGA design issues as well as outlines commonly-used design techniques leading to safe reset implementations. It goes on to explain about Reset Domain Crossing effects and methods to mitigate their influence on design. LINT tools provide valuable help for designers in Resets and Reset Domain Crossings verification. ALINT-PRO White Papers 4 results
