Documentation Search in Resources Articles Manuals -OR- All Products Active-HDL Riviera-PRO ALINT-PRO HES-DVM HES Proto-AXI HES™ Boards RTAX/RTSX Adaptor Boards HES-DVM Proto Cloud Edition TySOM™ EDK Spec-TRACER DO-254/CTS All Documents Application Notes Manual Demonstration Videos FAQ Recorded Webinars Tutorials White Papers Technical Specification Case Studies All Categories Coverage 3rd Party Integration Design Entry, Documentation Simulation, Debugging Design Management, Libraries Advanced Verification Assertions and Functional Coverage RTL Simulation & Verification HDL Languages Encryption Military & Aerospace Verification Design Rule Checking Design Hardware Emulation Solutions Encryption Design HDL Languages RTL Simulation & Verification Assertions and Functional Coverage Advanced Verification Design Rule Checking Military & Aerospace Verification Hardware Emulation Solutions Tutorials Prototyping High-Level Synthesis Embedded Embedded Embedded High Performance Computer SoC & ASIC Prototyping Reset Results Name Products Type Action #ELBREAD: Warning: Module 'module_name' does not have a `timescale directive, but previous modules do. Riviera-PRO FAQ ACOM: Error: COMP96_0153: Formal "name" of class variable must be associated with a variable Riviera-PRO FAQ ACOM: Error: ELAB1_0021: filename.vhd: Types do not match for port "port_name" Riviera-PRO FAQ Achieving RTL-to-Netlist Equivalence Simulation-to-Synthesis mismatch issues may cause malfunctions of physical devices. Even for functionally flawless RTL simulations, their physical implementation may contain critical design bugs. RTL Linting is the only way to locate and fix Simulation-to-Synthesis mismatch issues. The following article presents typical simulation-to-synthesis mismatch issues, illustrated by simple examples. For each one of described issues, the Lint checks are identified and explained. Active-HDL, Riviera-PRO, ALINT-PRO White Papers Advanced Dataflow Learn how to use Advanced Dataflow in Riviera-PRO Riviera-PRO Tutorials Assertions Learn how to use Assertions in Riviera-PRO Riviera-PRO Tutorials Basic use of SystemVerilog DPI-C in Riviera-PRO Riviera-PRO Application Notes Best Design Practices for High Capacity FPGA Devices With the latest FPGA technology advancements and release of large-scale FPGA devices, design teams are facing more challenges than ever in producing high quality HDL code. In order to save time during Functional Verification and Implementation stages, it becomes increasingly important to ensure the quality of design starting from the very early stages of the design process. In an ASIC design flow, a Lint tool (sometime referred to as Design Rule Checkers) ensures early-stage design quality, and maintaining this quality throughout the project lifecycle. Riviera-PRO, ALINT-PRO White Papers Code Coverage Learn how to use Code Coverage in Riviera-PRO Riviera-PRO Tutorials Code Coverage Visualization in GitLab Riviera-PRO Application Notes Combining Code Coverage and FSM Graph in Riviera-PRO to extract FSM debug information Riviera-PRO Application Notes Compile Xilinx ISE Libraries for Aldec using compxlib Active-HDL, Riviera-PRO Application Notes Compiling Intel® Quartus® Prime Simulation Libraries for Riviera-PRO Riviera-PRO Application Notes Compiling Multiple SystemC Libraries Active-HDL, Riviera-PRO Application Notes Compiling Xilinx Vivado Simulation Libraries for Riviera-PRO Riviera-PRO Application Notes Compiling altera_primitives.v (Quartus 11.1) in Riviera-PRO and Active-HDL Active-HDL, Riviera-PRO FAQ Components of XilinxCoreLib Library Are Missing after Migration to Xilinx Vivado Active-HDL, Riviera-PRO FAQ Controlling Riviera-PRO from MATLAB® Riviera-PRO Application Notes Debugging SCE-MI Co-Emulation in Riviera-PRO Abstract: Debugging a design during emulation with a high level of visibility can be a challenge. This paper presents Aldec’s solution to this problem; a debugging environment for SCE-MI co-emulation that provides 100% signal visibility of the design running in an FPGA-based emulator. Debug probes captured intelligently from emulator retain original signals names and hierarchy paths to provide true RTL view of design in emulation. Riviera-PRO, HES-DVM White Papers Debugging Tools Learn how to use Debugging tools in Riviera-PRO Riviera-PRO Tutorials 135 results (page 1/7)
