Documentation

The increasing adoption of large, high-pin-count and high-speed FPGA devices means that right-first-time printed circuit board (PCB) design practices are more essential than ever for ensuring correct system operation. Typically, the PCB design takes place concurrently with the design and programming of the FPGA. Signal and pin assignments are initially made by the FPGA designer, and the board designer must correctly transfer these assignments to the symbols used in their system circuit schematics and board layout. As the board design progresses, pin reassignments may be needed to optimize the PCB layout. These reassignments must in turn be relayed back to the FPGA designer so that the new assignments can be processed through updated placement and routing of the FPGA design. To overcome these challenges, Zuken and Aldec provide an integrated design environment to support these design flows.

This demo design uses TySOM-3-ZU7EV board to capture the LI_IMX274MIPI camera 4K video through the FMC HPC connector on the board and show it on a screen. LI-IMX274MIPI-FMC is a high-resolution digital camera board. It incorporates a Sony 1/2.5" CMOS digital image sensor with an active imaging pixel array of 3864H x2196V.

Growing customer requirements and technological abilities increase the design complexity of hardware and software. Time to market is shortening as well as the lifetime of new designs. In order to meet all those requirements a new approach to the design process is required.

This tutorial provides instructions for using the basic features of the Active-HDL simulator. Active-HDL is an integrated environment designed for development and verification of VHDL, Verilog, System Verilog, EDIF, and System C based designs. In this tutorial we use a Sample VHDL design called PressController from the Active-HDL installation to perform design entry and simulation.

This document describes running an HDL simulation using Active-HDL in the batch mode.

This document describes running an HDL simulation using Active-HDL in the GUI mode.

This document describes managing libraries in Active-HDL.

This tutorial explains what compilation and simulation options (switches) must be used to achieve the ultimate VHDL simulation performance.

This tutorial explains what compilation and simulation options (switches) must be used to achieve the ultimate Verilog simulation performance.

Active-HDL stores simulation results in a signal database file for easier design management.

The Advanced Dataflow window is a tool that allows you to explore the connectivity of a simulated design and analyze dataflow among instances, concurrent statements, VHDL signals and Verilog nets and variables. Values in the design logic can be traced back to their origin, and forward, to the design outputs.

An HDL code breakpoint can be set in HDL source files that are VHDL, Verilog, and SystemVerilog. A breakpoint can also be set in OVA and PSL code, for example in lines that contain assert or cover statements.

Active-HDL users have access o a rich set of debugging tools that enables quick ways to detect and diagnose design issues.

XTrace tool creates a report with information on unknown values in the simulated model.

Code Coverage aids the verification process by providing information in details whether and how the design is verified or which parts of the design are still untested.

Active-HDL provides a built-in interface that allows the integration of MathWork’s intuitive language and a technical computing environment with Aldec's HDL-based simulation environment.

The Simulink Interface built-into Active-HDL provides the integration of the Math Works' simulation tools with Aldec’s HDL-based simulation environment for FPGA and ASIC designs.

This tutorial explains how to use Assertions in Active-HDL.