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Name Products Type Action
Achieving RTL-to-Netlist Equivalence   
Simulation-to-Synthesis mismatch issues may cause malfunctions of physical devices. Even for functionally flawless RTL simulations, their physical implementation may contain critical design bugs. RTL Linting is the only way to locate and fix Simulation-to-Synthesis mismatch issues. The following article presents typical simulation-to-synthesis mismatch issues, illustrated by simple examples. For each one of described issues, the Lint checks are identified and explained.
Active-HDL, Riviera-PRO, ALINT-PRO White Papers
Aldec DO-254 Solutions Blueprint   
The Federal Aviation Administration (FAA) recognizes the use of commonly used tools for FPGA design and verification such as RTL Simulator, Synthesis, Place & Route and Static Timing Analysis. For DAL A and B FPGAs, the FAA also recognizes other tools that improve design, verification, traceability and project management including Requirements Management, Traceability, Tests Management, Design Rule Checker, Clock Domain Crossings (CDC) Analysis, Code Coverage and FPGA Physical Test Systems.
Active-HDL, ALINT-PRO, Spec-TRACER, DO-254/CTS White Papers
Best Design Practices for High Capacity FPGA Devices   
With the latest FPGA technology advancements and release of large-scale FPGA devices, design teams are facing more challenges than ever in producing high quality HDL code. In order to save time during Functional Verification and Implementation stages, it becomes increasingly important to ensure the quality of design starting from the very early stages of the design process. In an ASIC design flow, a Lint tool (sometime referred to as Design Rule Checkers) ensures early-stage design quality, and maintaining this quality throughout the project lifecycle.
Riviera-PRO, ALINT-PRO White Papers
Clock Domain Crossings in the FPGA World   
Clock domain crossing (CDC) issues cause significant amount of failures in ASIC and FPGA devices. As FPGA complexity and performance grows, the influence of CDC issues on design functionality grows even more. This paper outlines CDC issues and their solutions for FPGA designs. Various design techniques are presented together with real-life examples for Xilinx and Intel FPGA devices. More importantly, this paper summarizes the most important CDC guidelines for highly-reliable FPGA designs.
ALINT-PRO White Papers
Finding CDC Issues Before They Find You: Advanced CDC Verification for DO-254 Compliance   
Clock domain crossings (CDCs) in FPGAs represent a probabilistic opportunity for failure. Functional simulation and static timing analysis tools are insufficient. Finding and addressing metastability and data incoherence around CDCs require static and dynamic analysis of FPGA designs. Aldec ALINT-PRO-CDC provides enhanced confidence that CDCs are located and fully mitigated.
ALINT-PRO, ALINT-PRO-CDC White Papers
Resets and Reset Domain Crossings in ASIC and FPGA designs   
This white paper explains Reset-related ASIC and FPGA design issues as well as outlines commonly-used design techniques leading to safe reset implementations. It goes on to explain about Reset Domain Crossing effects and methods to mitigate their influence on design. LINT tools provide valuable help for designers in Resets and Reset Domain Crossings verification.
ALINT-PRO White Papers
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