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Name Products Type Action
Course 05 - VHDL Performance Optimizations   
This tutorial explains what compilation and simulation options (switches) must be used to achieve the ultimate VHDL simulation performance.
Active-HDL Tutorials
Course 06 - Verilog Performance Optimizations   
This tutorial explains what compilation and simulation options (switches) must be used to achieve the ultimate Verilog simulation performance.
Active-HDL Tutorials
Course 07 - Waveform Viewer   
Active-HDL stores simulation results in a signal database file for easier design management.
Active-HDL Tutorials
Course 08 - Advanced Dataflow   
The Advanced Dataflow window is a tool that allows you to explore the connectivity of a simulated design and analyze dataflow among instances, concurrent statements, VHDL signals and Verilog nets and variables. Values in the design logic can be traced back to their origin, and forward, to the design outputs.
Active-HDL Tutorials
Course 09 - HDE Based Debugging   
An HDL code breakpoint can be set in HDL source files that are VHDL, Verilog, and SystemVerilog. A breakpoint can also be set in OVA and PSL code, for example in lines that contain assert or cover statements.
Active-HDL Tutorials
Course 10 - Debugging Tools   
Active-HDL users have access o a rich set of debugging tools that enables quick ways to detect and diagnose design issues.
Active-HDL Tutorials
Course 11 - XTrace   
XTrace tool creates a report with information on unknown values in the simulated model.
Active-HDL Tutorials
Course 12 - Code Coverage (Statement, Branch, Toggle, Expression Coverage)   
Code Coverage aids the verification process by providing information in details whether and how the design is verified or which parts of the design are still untested.
Active-HDL Tutorials
Course 13 - MATLAB® Interface in Active-HDL   
Active-HDL provides a built-in interface that allows the integration of MathWork’s intuitive language and a technical computing environment with Aldec's HDL-based simulation environment.
Active-HDL Tutorials
Course 14 - Simulink® Interface in Active-HDL   
The Simulink Interface built-into Active-HDL provides the integration of the Math Works' simulation tools with Aldec’s HDL-based simulation environment for FPGA and ASIC designs.
Active-HDL Tutorials
Course 15 - Assertions   
This tutorial explains how to use Assertions in Active-HDL.
Active-HDL Tutorials
Creating a Hardware and Software Project to Blink LEDs TySOM -1-7Z030   
In this tutorial, you will learn how to create a hardware project in Xilinx’s Vivado Design Suite and create a software project in Xilinx’s SDK for the TySOM-1-7Z030 board. First you will create the hardware part, then you will create a software application to blink the onboard LEDs using standalone OS. In the Zynq architecture, you are able to implement the design either in a bare metal mode or by using an embedded Linux OS platform.
TySOM Tutorials
Creating a Hardware and Software Project to Blink LEDs using DIP Switches TySOM -1-7Z030   
In this tutorial, you will learn how to create a hardware project in Xilinx’s Vivado Design Suite and create a software project in Xilinx’s SDK for the TySOM-1-7Z030 board. First you will create the hardware part, then you will create a software application to blink the onboard LEDs using onboard switches. At the end of this tutorial, you will also learn how to program the project onto the TySOM-1-7Z030 board using a JTAG programmer. To program the FPGA using a microSD card, you can follow the “Programming the TySOM-1-7Z030 board using a microSD card guide”.
TySOM Tutorials
Debugging Tools   
Learn how to use Debugging tools in Riviera-PRO
Riviera-PRO Tutorials
DO-254 Requirements Traceability Tutorial   
This tutorial provides step-by-step instructions on how to use Spec-TRACER to meet the DO-254 objectives for requirements traceability.
Spec-TRACER Tutorials
Enabling GPIO Interrupts Tutorial TySOM-1-7Z030   
An interrupt is a signal that temporarily halts the processor’s current activities and demands immediate attention. The processor saves its current state and executes an interrupt service routine to address the reason for the interrupt. Real-time designs require interrupts because many systems will have a number of inputs (e.g. keyboards, mouse, pushbuttons etc.) that will require processing. Inputs from these devices are generally asynchronous to the execution of running processes or tasks, so you cannot always predict when the event will occur. Using interrupts enables the processor to continue processing until an event occurs, at which time the processor can address the event. This interrupt-driven approach also speeds up the response time. This basic GPIO interrupt design is intended to enable GPIO interrupts to users on the TySOM-1-7Z030 board. The standard flow includes several stages to create a hardware platform for the Zynq-7000 based board.
TySOM Tutorials
HDE based debugging   
Learn how to debug your code in Riviera-PRO
Riviera-PRO Tutorials
IoT Demo Application Tutorial - TySOM-1-7Z030   
Internet usage has expanded to a new mode: device to device. This new mode is used in Internet of Things (IoT) applications and devices are called IoT gateways. The Aldec TySOM contains a Zynq-7000 SoC with ARM processor and a variety of interfaces to be utilized as an IoT gateway device. This document provides all necessary information about the Aldec IoT demo project with the TySOM-1-7Z030 board.
TySOM Tutorials
Library Management   
Learn how to manage Libraries in Riviera-PRO
Riviera-PRO Tutorials
Programming the TySOM-1-7Z030 Board Using a MicroSD Card   
In this tutorial, you will learn how to run your hardware and software application on the TySOM-1-7Z030 board using a microSD card as the boot method. The microSD card is used when you want your application to be persistent despite any power cycling. In this situation, the board will boot from the microSD card.
TySOM Tutorials
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