Disable Timing Check Message during Timing simulation using Design Flow.


I am trying to run timing simulation using The Design Flow of Active-HDL. The options to disable timing check messages under Design | Settings | Simulation menu does not seem to work. How can I disable timing check messages if I am using the Design Flow?


  1. Go to your timing simulation options in the Design flow window

  2. In the dialog window, click on the Generate DO Macro button.

  3. Name the new file and click OK. The new .do file will be added to your Design browser window

  4. Open this .do file and add +no_tchk_msg to the asim command

  5. Right click on the .do file in Design browser and select Execute option

This should disable the message from being displayed.

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