Simulating Xilinx MicroBlaze design in Riviera-PRO Simulator

Introduction

This Application Note describes how to use Aldec's Riviera-PRO to simulate a Xilinx MicroBlaze design.

This Application note assumes that you have created the hardware part of your embedded system as well as the software to run on it in Xilinx ISE and EDK and that you have built your embedded design in Xilinx Platform Studio and integrated it with ISE project. Your complete chip level project in ISE may include non-XPS based blocks. Further, we will explain how to simulate your complete Xilinx ISE design (which may include both XPS and non-XPS blocks) in Riviera-PRO.

To simulate your system you will need to generate a simulation model of your embedded design. Follow steps to generate simulation models

  1. Before you can generate a simulation model for your embedded design, you have to get EDK simulation libraries provided by Aldec for Riviera-PRO.

  2. Click on http://www.aldec.com/en/downloads to get the library package.

  3. Log in to portal using your email ID and password. If you are not registered then please register using ‘Register’ button on same page.

  4. Once you are logged in, click on Riviera-PRO > version number (e.g. 2012.06) > select your OS (e.g. windows64) > XILINX LIBRARIES

  5. Now download EDK library (.zip file) matching your ISE version and Riviera-PRO version.

  6. If you cannot find the necessary library version please submit your request to Aldec support team by opening a support case at http://www.aldec.com/support/index.php with the version number of EDK and Riviera-PRO that you intend to use.

  7. Once the EDK library package is received, extract it from the zip archive and store it on the local disk. e.g. C:/My_Designs/Xilinx_EDK_Sources/EDK

You can then use Riviera-PRO to simulate your embedded system design at behavior level.

Simulating ISE and XPS design in Riviera-PRO

Installing EDK Simulation Libraries in Riviera-PRO

Start Riviera-PRO, change your present working directory to where you have stored EDK library (see instruction above) and go to menu Tools | Execute macro then navigate to the folder with EDK source (src), point to compedklib.do macro and click on Open button. Upon execution of this macro your Xilinx EDK libraries will compiled for Riviera-PRO.

Set Riviera-PRO as the default simulator in ISE Project Navigator

  1. Go to ISE menu Edit | Preferences and select Integrated Tools under ISE General.

  2. Click the browse button for the Model Tech Simulator and point to Riviera-PRO’s ‘vsim.exe’ located in the Riviera-PRO\bin (installation directory) folder.

  3. Now go to ISE menu Project | Design Properties.

  4. Select HDL option under Top-Level Source File and ‘Modelsim-SE’ Mixed option under Simulator.

    Now, we need to set some advanced simulator properties.

  5. Make sure that Simulation view is selected in ISE Design tab. Then in the Processes tab you need to right click on Simulate Behavioral Model and select Process Properties.

  6. In Simulation Properties window, select Simulation Properties on the left and then enter ‘+access +r’ under Other VSIM Command Line Options. This will allow you to trace your design signals later in the Riviera-PRO's waveform window.

  7. In Compiled Library Directory option provide path to EDK library which you stored on your disk in above steps (Installing EDK Simulation Libraries For Riviera-PRO)

Generating simulation files under ISE

  1. Switch to Implementation view in Design tab of ISE and synthesize your design by running Synthesize-XST process. This is necessary even for behavioral simulation because some blocks such as MicroBlaze can only be simulated as a netlist in Riviera-PRO.

    Note: Simulating MicroBlaze module as a netlist does affect neither the visibility nor the speed of the simulation.

    Once the synthesis is over you will get several .ngc files in your design directory. Now we will have to generate an HDL simulation model from netlist for the MicroBlaze block.

  2. Once the synthesis is over you will get several .ngc files in your design directory. Now we will have to generate an HDL simulation model from netlist for the MicroBlaze block.

  3. Go to Windows OS Start menu and launch ISE Design Suite Command Prompt under All Programs | Xilinx ISE Design Suite | Accessories.

  4. Change directory (with cd command) to your project directory where you have the ngc netlist file for MicroBlaze (e.g. microblaze_0_wrapper.ngc).

  5. Type one of the following commands to generate simulation file for the processor core in either Verilog or VHDL format: For Verilog:

    > netgen –intstyle ise –w –ofmt  verilog –sim microblaze_0_wrapper.ngc microblaze_0_wrapper_netlist.v
    

    For VHDL:

    >netgen –intstyle ise –ar structure –w –ofmt vhdl –sim microblaze_0_wrapper.ngc microblaze_0_wrapper_netlist.vhd
    

Starting the simulation from ISE

  1. Inside the ISE Design | Hierarchy window select set the View to Simulation.

  2. Select your system top level entity in the Design window. After that you will be able to see Modelsim Simulator | Simulate Behavioral Model in the Processes window.

  3. Right click on Simulate Behavioral Model and select Run. This will launch and start your simulation in Riviera-PRO.

  4. If you get errors in Riviera-PRO during compilation process perform the following changes:

    • Open <XPS_project_name>.do macro file located in your main ISE project directory and replace the reference to microblaze_0_wrapper.vhd with the file that we generated above microblaze_0_wrapper_netlist.vhd (likewise for Verilog designs).

    • Remove ‘–novopt’ switch from all ‘vlog’ and ‘vcom’ commands located in <XPS_project_name>.do macro file

    • Remove ‘–novopt’ switch from ‘vsim’ command located in <ISE_design_name>.fdo macro file

    • Need to comment out ‘view signals’ command from <ISE_design_name>.fdo macro file

    • Rename <ISE_design_name>.fdo file to <ISE_design_name>.do

      Note: <XPS_project_name> means this file name depends on your XPS project name and <ISE_design_name> means this file name depends on top level file from ISE project. So depending upon these names script (macro) name can differ.

  5. Once you perform changes you can start the process of compilation and simulation again in Riviera-PRO by executing the <ISE_design_name>.do macro. The name of the <ISE_design_name>.do macro file is your top level file or instance dependent which you just renamed in above step.

  6. Right click on the <ISE_design_name>.do macro in Riviera-PRO's File Browser and select Execute.

  7. Upon successful execution of the .do macro your simulation will start and you will be able to observer your waveforms.

Ask Us a Question
x

Ask Us a Question

x
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.