Aldec to Demonstrate UVM Simulation Acceleration with Network-On-Chip (NoC) Demo Design at DVCon U.S. 2017

Date: Feb 23, 2017Type: Release

Henderson, Nev. – February 23, 2017 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, will present its ASIC pre-silicon Verification Spectrum with hardware-in-the-loop at the DVCon U.S. Conference and Exhibition to be held February 27 – March 2, 2017 in San Jose, California. 


UVM Simulation Acceleration

Aldec’s 30+ years expertise in HDL simulation and deep understanding of contemporary SoC design/verification demands has paved the way to Aldec’s high-performance HDL simulator, Riviera-PRO™, supporting UVM, SystemVerilog, OSVVM, VHDL-2008 and TLM/SystemC. With Riviera-PRO running with hardware-in-the-loop, the simulation can even be two orders of magnitude faster. The live demo to be presented at DVCon U.S. will demonstrate how to achieve over 130x of simulation acceleration with an example Network on Chip (NoC) design running on a Aldec HES™ FPGA-board driven by a transaction-level UVM Testbench executed in Riviera-PRO. Visitors will have an opportunity to learn about a systematic approach to build universal UVM drivers and monitors as SCE-MI transactors that can be used both in pure simulation and mixed simulation/emulation environments. The latest Riviera-PRO release also provides SCE-MI Code Templates to enable quick development of SCE-MI compliant transactors containing SV DPI-C functions, macros and pipes. Visitors will also learn how to create an ad-hoc transactor for simulation and emulation in minutes, debunking the myth that architecting a testbench for emulation is overwhelming.

“Aldec has perfected an approach where the structure of UVM components does not need to be modified. We have automated the generation of the SystemVerilog DPI-C transaction layer C code based on the SCE-MI SV-Connect guidelines and developed a SCE-MI Compiler for converting the necessary DPI-C functions/tasks to synthesizable code for the emulator,” said Krzysztof Szczur, Aldec Hardware Verification Products Manager. “All of this simplifies the usage and interoperability of the UVM Testbench between simulation and emulation, enabling users to achieve the highest verification functionality, coverage and performance."

“At the first DVCon Conference of 2017, Aldec will also announce the availability of the new HES board which is based on the largest Xilinx® Virtex™ UltraScale™ FPGAs US440,” said Louie De Luna, Aldec Director of Marketing.  “This board is a unique combination of the largest UltraScale FPGA module with the Zynq™-7000 device that can be used to implement an embedded testbench executed by the ARM® Cortex™ processor or serve as a host workstation controller with PCI Express interface. 


About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification, Embedded Solutions and Military/Aerospace solutions. www.aldec.com

Media Contact:          
Christina Toole, Aldec, Inc.                             
+ (702) 990-4400

Better Code With RTL Linting And CDC Verification

Date: Feb 23, 2017Type: In the News

By Sergei Zaychenko 


Automated design rule checking, or linting, has been around in RTL verification for at least a couple decades, yet still many HDL designers completely ignore this simple yet very powerful bug hunting method. Why would a busy designer need to run this annoying warning generator? The hostility against using conventional linting tools is often explained by the enormous amount of output noise, limited configurability, ambiguous reporting, and inability to capture a high-level designer’s intent. FPGA users also complain about the lack of vendor libraries support. Whether it’s an ASIC or FPGA, the presence of IP blocks creates an extra challenge for DRC tools, as IPs are often tool-generated or encrypted.


While there are a couple of well-known, mature DRC-based verification tools on the EDA market targeting the large-scale ASIC segment, they also come with an annual license cost that exceeds the price of a new four-wheel SUV. The use of auto-formal methods applied to aspects such as CDC protocol checks and MCP validation, as well as the handling of UPF-based power models and taking physical cell properties into account, indeed make those linting tools very powerful. But is this capacity really necessary for a hypothetical mid-range FPGA project relying on the native vendor’s backend implementation tools...


For the rest of this article, visit SemiConductorEngineering.

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