Biggest Hits and Trends from ARM TechCon

Emulation, Beer, and the Latest Processors

Bill Jason P. Tomas, Product Engineer, Hardware Division
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The recent ARM® TechCon Conference in Santa Clara was definitely the front-runner of my favorite conferences that I attended this year. Fun, informative and filled with software engineers, physical designers, design verification teams, and hardware engineers – ARM TechCon was the place to be to learn about the latest innovations from the embedded industry. Aldec was there showcasing our HES-DVM™ and HES-7™ platforms, which enable engineers to utilize emulation and FPGA-based prototyping to verify the latest ARM designs. 

 

110613_img_01_350_01One of the biggest trends I observed from EDA vendors at TechCon was Emulation with the latest and greatest ARM processors (bigLittle, Cortex, etc.). A major issue designers are facing is OS bootup – so incorporating Virtual Platforms and ARM models with emulation platforms was definitely a hot topic at the Aldec booth.  Also, In-Circuit Emulation (ICE) was gaining recognition for allowing verification teams to utilize real-time interfaces with their emulation platforms. Aldec showcased the HES-7 SoC DB, which utilizes a Xilinx® Zynq™ SoC with dual-core ARM Cortex®-A9 processors, and demod a Linux bootup running a simple Hello World to the user.

 

110613_img_02_307The event also included a festive evening Beer Garden which featured live music, games, food and of course, beer. We had a great time visiting with attendees that lined up to play hoops at the Aldec booth for a cold microbrew, as each had to “win” a beer with a successful basket. The ARM Techcon organizers definitely did a great job with the Beer Garden event, as everyone seemed to enjoy the laid back atmosphere after a day of exhibits, discussions, and technical demonstrations.

So what was my major takeaway from this year’s ARM Technical Conference? Verification of ARM-based processors is vital in the SoC design process. Gone are the days in which RTL simulation of block-level designs were sufficient, people need more! New methodologies such as Co-Emulation, ICE, Virtual Platforms, Higher levels of abstraction, and Hybrid platforms are paving the future of verification. With the HES hybrid HW/SW verification platform, Aldec will continue to provide growth and support for the new and upcoming challenges faced by tomorrow’s verification teams. For more on HES, visit www.aldec.com/products/hes-dvm.

 

Bill is responsible for Aldec Hardware Emulation and SoC / ASIC Prototyping. He received his B.S. in Computer Engineering from Auburn University in Alabama in 2011, and currently undertaking his M.S in Electrical Engineering with a focus on hardware emulation methodology and Built-In-Self-Test for high capacity FPGAs. He is also currently a graduate research assistant for the University of Nevada Systems and Integration laboratory studying Network-on-Chip BIST strategies. 

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