Simplify your FPGA Verification

New Tools for Comprehensive Debugging

Satyam Jani, Product Manager Software Division
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Time and effort spent on FPGA debug and verification is already considerably high and only increasing. The complexity of today's FPGA device has increasingly grown, the size of designs making it challenging to leverage the in-hardware testing approach. At the same time, fierce competition is shrinking time-to-market requirements. This makes it difficult for designers to use the legacy approach of implement-and-test designs in hardware. While most FPGA vendor tools provide solutions for basic simulation to adequately support their low density devices, these tools lack the powerful debugging and verification needed to allow designers to be competitive in meeting schedules and efficiently debugging large scale FPGAs.

Aldec has recently added tools to explore dataflow and connectivity in FPGA designs, including X-value detector and Code Coverage to enable FPGA designs a comprehensive debugging environment.

X-Trace. Monitoring unknown values during simulation is a time challenging task, especially when simulation runs for an extended amount of time.In a typical scenario, any unknown values that appear during the simulation will propagate through the design and will be visible at the end of the simulation. X-traceThis in turn requires designers to trace back to the source of the issue, a time-consuming task as unknown values may have propagated deep down in the hierarchy. X-Trace is the debugging tool that allows designers to detect and report unknown values right when they appear during simulation. It reports unexpected values, signals and the time when those values were detected, providing designer more time to fix the actual issue rather than searching for it.

 

Advanced Dataflow is a useful graphical debugging tool that identifies an unexpected Advanced Dataflowoutput by graphically tracing the events that may have propagated through design. It is often used to debug the design during simulation for tracing signal values and exploring the physical connectivity of the design.

 

Code Coverage tools for metric based verification, which is required by most verification plans, are very common in today's FPGA design development flow.

Code CoverageCode coverage measures how much code is checked by the testbench, providing information about dead code in the design and holes in test suits. Code coverage also helps improve the predictability and quality of the test environment. Popular code coverage types that are used by designers around the world include Statement/Branch Coverage, Expression/Condition Coverage and Path Coverage.

 

Active-HDL has now enabled all of these features in its Plus Edition configuration at no cost. Current Active-HDL users are encouraged to obtain an updated license to take advantage of these powerful debugging features.

Related Movies for more information: Code Coverage, Advanced Dataflow, X-Trace.

Satyam manages Aldec’s leading FPGA design entry and simulation tool – Active-HDL. He received his B.S. in Electronics Engineering from Sardar Patel University, India in 2003 and M.S in Electrical Engineering from NJIT, New Jersey in 2005.  His practical engineering experience includes areas in Solid state electronics, Digital Designing and functional verification. He has worked in wide range of engineering positions that include FPGA Design Engineer, Applications Engineer and Product Manager.

  • Products:
  • Active-HDL
  • FPGA Design Simulation

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