Fast Track™ to SystemVerilog for Verilog Users

Many experienced Verilog users tend to ignore SystemVerilog - mainly because high-end verification features of the new language are getting the majority of the  attention in the press, and at conferences and trade shows. Those users may not realize that there are many SystemVerilog features that are very useful for them, no matter if they are writing synthesizable code or regular testbenches.

Fast Track™ to SystemVerilog for Verilog Users is a free, online training which assumes solid working knowledge of classic Verilog and shows all SystemVerilog enhancements that can be used in everyday coding. The first section of this training (suitable for all designers) is available now in Aldec’s Fast Track ONLINE™  training portal. The second section (coming soon) will provide gentle introduction to randomization, coverage, assertions, programs and similar advanced topics.

Fast Track ONLINE™ is available at no cost to all aldec.com registered users and features a series of private, online training modules. Each module allows the user to go back to review material and ends with quick self-test before proceeding to ensure the material is grasped before proceeding.

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