Building an Efficient Clock Network

For FPGA-Prototyping Boards

Bill Jason P. Tomas, Product Engineer, Hardware Division
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Developing an in-house prototyping board requires a large investment in time, knowledge, and resources.  Going down the “build-your-own” route does, however, provide advantages such as: the ability to add personalized interfaces, manufacture the board for different goals (speed, power, flexibility), and reduced cost compared to buying an off-the-shelf board. One large issue designers face is developing an efficient clock network from resources available on the FPGAs and board-level clock resources which will provide flexibility to designers.

On-Board Clock Resources

Modern FPGAs provide an array of clock resources such as PLLs for scaling of clock frequencies and multiple clock domains, however this is only helpful for systems which are able to fit into a single chip. Today’s SoC’s are not always able to fit onto a single FPGA and must be partitioned across several to fit onto a prototyping environment. Multiple FPGA boards require a full hierarchy of clocking functionality such as clock multiplexers, divers and multipliers, board clock synchronization, and board-level clock input. There are techniques to cut down on the complexity of the task such as gated clock conversions. ASIC designs typically implement gated clocks to cut down on the switching activity of the system clock, greatly reducing power. However, this does not translate well in the FPGA environment which would require clock enables instead of gates clocks, which can present timing issues.


Designing a flexible clock network requires a close look at system requirements which may include:

1. Matching clock delays
2. PLLs
3. Clock Synchronization and Generation
4. Clock Control and Configuration

Each of these requirements is a large task upon itself, in which the designer may include multiple clock elements such as source selectors, special high-speed clocks (GTX links), external clock sources, and scalars to solve multiple issues while providing flexibility. It may be tempting to some designers to develop a board specifically for clock resources to simply the complexity, which increase design can cost and silicon real-estate. However, a board without an adequate amount of flexibility places a greater restriction on the partitioning decisions more large designs.

HES-7 Configurable Clock Resources

The HES-7 clock scheme is comprised of low-skew global clock networks with user programmable PLLs and MMCX clock connectors. Included on the board are five clock oscillators ranging from 192 MHz to 500 MHz, and external differential clock inputs up to 450 MHz. To provide global clock connection to the board, five global clock inputs are provided via backplane connector (capable of speeds up to 25 GB/s). Dedicate clock circuitry is allocated for the GTX lines and PLL module to simplify signal configuration. Both clock schemes shown above below for GTX lines and PLL module.


Figure 1: CLK_GTX clocking scheme block diagram


Figure 2: CLK_PLL clocking scheme block diagram

For Technical Specifications and more on the HES-7 ASIC Prototyping Platform, visit /products/prototyping/hes-7.

Bill is responsible for Aldec Hardware Emulation and SoC / ASIC Prototyping. He received his B.S. in Computer Engineering from Auburn University in Alabama in 2011, and currently undertaking his M.S in Electrical Engineering with a focus on hardware emulation methodology and Built-In-Self-Test for high capacity FPGAs. He is also currently a graduate research assistant for the University of Nevada Systems and Integration laboratory studying Network-on-Chip BIST strategies. 


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