Event Details View All Recorded Events Date Event Type 場所 Action May 21, 2026 Making a Simple VHDL Testbench Step-by-Step Part 1: Foundations, Architecture and Basics (US) Time: 11:00 AM - 12:00 PM (PDT) Webinar Overview Most simple testbenches have close to no structure, are terrible to modify and hopeless to understand. On top of that, they take far too much time to implement and provide close to no support when debugging potential problems. In this first part of the 2-part webinar series, we start by looking at simulation in general and what needs to be verified for a very simple interrupt controller DUT. We will then look at the verification stages, the TB infrastructure and architecture, and verbosity control. The presentation will show how to make a simple testbench from scratch and introduce a good, modern testbench approach. We will cover logging, checking values, handling time-related aspects, and working with signal changes and stability. Commands from UVVM are introduced to show the principles and what you can and should do, but the presentation is not tool dedicated. Rivera-PRO comes with a pre-compiled version of the latest UVVM, thus it is extremely easy to get going with UVVM after this webinar. UVVM is currently being used by more than 27% of all FPGA designers worldwide. Extensions are being developed in tight cooperation with the European Space Agency (ESA) and are thus targeted for simple but efficient verification – for both FPGA and ASIC. Agenda: Why testbenches and simulation Achieving flexibility, readability, extendibility The simple Interrupt Controller DUT Verification stages TB infrastructure and architecture Verbosity control Logging and checking values and time aspects Q&A Presenter BIO Espen Tallaksen, CEO of EmLogic, NorwayEspen is also the author and architect of the Open Source UVVM (Universal VHDL Verification Methodology), andhas a strong interest in methodology cultivation and pragmatic efficiency and quality improvement.He has given lots of technical presentations at various international conferences with great feedback. He is also giving courses on FPGA Design and Verification worldwide. ウェブセミナー Online More Info
