Event Details View All Recorded Events Date Event Type 場所 Action Sep 04, 2025 Advanced Static Linting Techniques for High Performance Design Optimization (US) Time: 11:00 AM - 12:00 PM (PST) Abstract Next generation high-speed FPGA families such as AMD® Virtex™ Ultrascale+ and Altera® Agilex™ 7 are built for applications demanding exceptional processing power and data throughput. Achieving this performance requires not only higher clock frequencies but also carefully optimized RTL designs. Advanced linting is a static HDL code analysis process that detects hidden issues in RTL code by checking it against hundreds of design rules. Beyond improving code quality, advanced linting directly contributes to performance optimization: a critical factor in meeting frequency, power, and area targets for highspeed FPGA designs. ALINT-PRO provides an extensive set of performance-oriented rules that help engineers identify and fix potential bottlenecks early in the design cycle. Addressing these issues up front can significantly reduce or eliminate lengthy implementation and timing closure iterations within FPGA vendor tools. These design rules are categorized as follows: RTL statements optimization Arithmetic operators’ efficiency Proper design partitioning techniques RTL optimizations for timing closure This webinar will showcase how to apply these rules effectively using real design examples. We’ll also demonstrate how early-stage performance optimization with ALINTPRO can streamline timing closure in Vivado™ and accelerate overall project schedules. Agenda: Advanced Linting process Overview RTL Performance optimization methods: Power, Area optimization Timing optimization ALINT-PRO Performance optimizations RTL statements optimization Arithmetic operator optimization Proper design partitioning guidelines RTL optimization for timing closure Design Example with ALINT-PRO and Vivado Conclusion Q&A Presenter BIO Alex Gnusin, Aldec’s ALINT-PRO Product Manager Alex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM, Nortel, Ericsson and Synopsys Inc, he combined various verification methods such as static linting, formal property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology. ウェブセミナー Online More Info
