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Oct 05, 2023 FPGA Design Verification in a Nutshell

Part 3: Advanced Verification Methods (US)

Time: 11:00 AM - 12:00 PM (PDT)



As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA teams are adopting advanced design verification methodologies and techniques to develop homegrown verification processes.


In this three-part webinar series, we will discuss design verification with a focus on creating an advanced simulation-based verification process; from verification planning and team organization, and moving on to regression setup, functional coverage collection, randomization and ‘verification done’ definitions. We will also show you how to develop simple yet powerful and reusable testbenches using Verilog and SystemVerilog constructs and how to functionally verify designs in the most efficient way.


In this, the concluding episode of the webinar series, we will present advanced verification solutions for verifying complex design properties. We will talk about randomization, functional coverage, and the importance of code coverage to achieve overall design verification completeness. Also, we will provide an overview on other important topics such as assertion and transaction-based verification and debug, static design verification with linting tools and regressions support. Finally, we will talk about ‘Verification Done’, in terms of at what point can the verification be considered complete and how do we achieve it?



  • Checkers and Scoreboards Development
  • Randomization Methods
  • Functional Coverage and Tests Grading
  • Code Coverage
  • Assertion-based Verification
  • Transaction-based Debugging with Riviera-PRO
  • Static Verification with Linting tools
  • Setting up Regressions
  • Defining “Verification Done”
  • Packet-based Design Verification Example
  • Conclusion
  • Q&A

Webinar Duration:

  • 45 min presentation/live demo
  • 15 min Q&A


Presenter BIO

Alexander Gnusin, Design Verification Technologist, Aldec

Alexander Gnusin accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM, Nortel, Ericsson and Synopsys Inc, he combined various verification methods such as static linting, formal property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology.


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