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Date Event Type 場所 Action
Dec 02, 2021 How to Simplify the Verification of Bus Interfaces (EU)

Time: 3:00 PM - 4:00 PM CEST

 

 

Abstract:

Today’s FPGAs and SoC FPGAs use various types of bus interconnect - such as AXI, APB, AHB, Avalon or Wishbone - for both internal (IP-level) and external communication. A recently added feature to Aldec’s ALINT-PRO allows designers to extract, review and verify the correctness of bus interface connections. In addition, ALINT-PRO is capable of automatically connecting bus protocol checkers and can monitor the current design to enable functional interconnect verification in simulation.

This webinar presents the bus interfaces extraction technology within ALINT-PRO. The concept of bus interface/interconnect instances will also be discussed. In addition, bus interfaces/interconnects visualization will be demonstrated with the new Interconnect Viewer and the enhanced Elaboration Viewer within ALINT-PRO. The automated process of “non-intrusive” protocol checkers and monitors attachment to design will be presented too.

 



Agenda:

  • An overview of bus interfaces and their types
  • Introduction to bus interconnects
  • Visualization of bus interfaces in ALINT-PRO
  • Static verification of bus interconnects with ALINT-PRO
  • Dynamic bus interconnects verification using auto-connected protocol checkers 
  • Live demo
  • Conclusion
  • Q&A

 

Presenter BIO

Alexander Gnusin, Design Verification Technologist. Alex accumulated 25 years of hands-on experience in various aspects of ASIC and FPGA design and verification. His employees list includes IBM, Nortel, Ericsson and Synopsys Inc. As Verification Prime for a multi-million gates project, he combined various verification methods - LINT, Formal Property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology.

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