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Building and Configuring a Linux OS using the Yocto Project - TySOM-1-7Z030   
This document describes the process for building an embedded Linux OS for the Aldec TySOM platform using the Yocto project, an open source collaboration project for creating custom Linux-based systems
TySOM Tutorials
Code Coverage   
Learn how to use Code Coverage in RIviera-PRO
Riviera-PRO Tutorials
Course 01 - Getting Started With Active-HDL   
This tutorial provides instructions for using the basic features of the Active-HDL simulator. Active-HDL is an integrated environment designed for development and verification of VHDL, Verilog, System Verilog, EDIF, and System C based designs. In this tutorial we use a Sample VHDL design called PressController from the Active-HDL installation to perform design entry and simulation.
Active-HDL Tutorials
Course 02 - Running Simulation in the Batch Mode   
This document describes running an HDL simulation using Active-HDL in the batch mode.
Active-HDL Tutorials
Course 03 - Running Simulation in GUI Mode   
This document describes running an HDL simulation using Active-HDL in the GUI mode.
Active-HDL Tutorials
Course 04 - Library Management   
This document describes managing libraries in Active-HDL.
Active-HDL Tutorials
Course 05 - VHDL Performance Optimizations   
This tutorial explains what compilation and simulation options (switches) must be used to achieve the ultimate VHDL simulation performance.
Active-HDL Tutorials
Course 06 - Verilog Performance Optimizations   
This tutorial explains what compilation and simulation options (switches) must be used to achieve the ultimate Verilog simulation performance.
Active-HDL Tutorials
Course 07 - Waveform Viewer   
Active-HDL stores simulation results in a signal database file for easier design management.
Active-HDL Tutorials
Course 08 - Advanced Dataflow   
The Advanced Dataflow window is a tool that allows you to explore the connectivity of a simulated design and analyze dataflow among instances, concurrent statements, VHDL signals and Verilog nets and variables. Values in the design logic can be traced back to their origin, and forward, to the design outputs.
Active-HDL Tutorials
Course 09 - HDE Based Debugging   
An HDL code breakpoint can be set in HDL source files that are VHDL, Verilog, and SystemVerilog. A breakpoint can also be set in OVA and PSL code, for example in lines that contain assert or cover statements.
Active-HDL Tutorials
Course 10 - Debugging Tools   
Active-HDL users have access o a rich set of debugging tools that enables quick ways to detect and diagnose design issues.
Active-HDL Tutorials
Course 11 - XTrace   
XTrace tool creates a report with information on unknown values in the simulated model.
Active-HDL Tutorials
Course 12 - Code Coverage (Statement, Branch, Toggle, Expression Coverage)   
Code Coverage aids the verification process by providing information in details whether and how the design is verified or which parts of the design are still untested.
Active-HDL Tutorials
Course 13 - MATLAB® Interface in Active-HDL   
Active-HDL provides a built-in interface that allows the integration of MathWork’s intuitive language and a technical computing environment with Aldec's HDL-based simulation environment.
Active-HDL Tutorials
Course 14 - Simulink® Interface in Active-HDL   
The Simulink Interface built-into Active-HDL provides the integration of the Math Works' simulation tools with Aldec’s HDL-based simulation environment for FPGA and ASIC designs.
Active-HDL Tutorials
Course 15 - Assertions   
This tutorial explains how to use Assertions in Active-HDL.
Active-HDL Tutorials
Creating a Hardware and Software Project to Blink LEDs TySOM -1-7Z030   
In this tutorial, you will learn how to create a hardware project in Xilinx’s Vivado Design Suite and create a software project in Xilinx’s SDK for the TySOM-1-7Z030 board. First you will create the hardware part, then you will create a software application to blink the onboard LEDs using standalone OS. In the Zynq architecture, you are able to implement the design either in a bare metal mode or by using an embedded Linux OS platform.
TySOM Tutorials
Creating a Hardware and Software Project to Blink LEDs using DIP Switches TySOM -1-7Z030   
In this tutorial, you will learn how to create a hardware project in Xilinx’s Vivado Design Suite and create a software project in Xilinx’s SDK for the TySOM-1-7Z030 board. First you will create the hardware part, then you will create a software application to blink the onboard LEDs using onboard switches. At the end of this tutorial, you will also learn how to program the project onto the TySOM-1-7Z030 board using a JTAG programmer. To program the FPGA using a microSD card, you can follow the “Programming the TySOM-1-7Z030 board using a microSD card guide”.
TySOM Tutorials
Debugging Tools   
Learn how to use Debugging tools in Riviera-PRO
Riviera-PRO Tutorials
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