SystemVerilog IEEE 1800-2012 (Design)

Category : Supported Standards

SystemVerilog is a set of extensions to the Verilog HDL that allow higher level of modeling and efficient verification of large digital systems. Originally developed by Accellera, SystemVerilog was standardized as IEEE Std. 1800™-2012. Merging of SystemVerilog and Verilog into one standard is planned in near future. Aldec supports SystemVerilog (IEEE Std. 1800™-2012) in three areas: hardware description extensions, assertions and advanced verification. The design portion of the standard includes mainly synthesizable constructs and the constructs for the behavioral modeling.

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