Riviera-PRO EDU Configurations

Marketing Features EDU Edition
Supported Standards
EDIF 2 0 0
Simulation of netlist in EDIF 2 0 0 format is supported by most Aldec Simulators.More >>
SystemVerilog IEEE 1800 - 2012 (Design)
SystemVerilog is a set of extensions to the Verilog HDL that allow higher level of modeling and efficient verification of large digital systems.More >>
Ref. Note (1) and (2)
Verilog® HDL IEEE 1364 (1995, 2001 and 2005)
ALDEC simulators provide full support of the IEEE 1364-2005 Standard. To enable simulation of a large variety of Verilog designs, both legacy and new, ALDEC simulators can be set to work in Verilog ’95, 2001 and 2005 modes.More >>
Ref. Note (1) and (2)
VHDL IEEE 1076 (1993, 2002, 2008 and 2019)
ALDEC simulators provide full support of the IEEE 1076-1993 Standard, IEEE 1076™-2002 VHDL standard and majority of just published IEEE 1076™-2008 Standard.More >>
Ref. Note (1) and (2)
Mixed Language
Mixed LanguageMore >>
Verilog Programming Language Interface (PLI/VPI)
The Verilog PLI (Programming Language Interface) and VPI (Verilog Procedural Interface) provide a standard mechanism to access and modify data in a simulated Verilog model.More >>
VHDL/Verilog Synplicity Compatible Encryption
VHDL/Verilog Synplicity Compatible EncryptionMore >>
Debug and Analysis
Accelerated Waveform Viewer
Accelerated Waveform ViewerMore >>
Advanced Breakpoint Management
Simulations can be stopped on a breakpoint. Aldec supports both breakpoints in the source code as well as signal breakpoints.More >>
HDL and Text Editor
HDL and Text EditorMore >>
Interactive Code Execution Tracing
Stepping through source code is one of the most common debugging procedures. Stepping is executing code one line at a timeMore >>
Language Assistant with Templates and Auto-complete
Language Assistant with Templates and Auto-completeMore >>
Floating License
The network floating configuration (multiple users) is based on a license started on a remote machine (license server) running on the Windows or Linux platform.More >>
Ref. Note (1) and (2) - Simulation performance limitations compared to full commercial release of Riviera-PRO:
Performance Restrictions: 4x slow down
Capacity Restrictions: 20,000 instances - 20x slow down.

Printed version of site: www.aldec.com/en/products/university_programs/riviera_pro_edu/configuration