Aldec Customer Testimonials "Riviera-PRO's UVM and SystemVerilog compliance and straightforward CI integration have since made it a dependable part of our verification flow. For a small engineering company contributing to a project of this scale, reusing verification IP rather than rebuilding it was a game changer." - Michal HUSEJKO About MHRL Sàrl MHRL Sàrl is a Geneva-area engineering company that designs and implements FPGA-based data acquisition and processing systems for institutional and industrial clients, working from edge to cloud with the customer's choice of FPGA fabric. MHRL SàrlRoute du Grand-Lancy 81CH-1212 Grand-Lancy, Switzerlandwww.mhrl.ch Aldec Tools: Riviera-PRO "This story starts at Stanford University, where a self-checking, UVM-based simulation environment was built to verify firmware for the Fast TracKer (FTK), a trigger upgrade project of the ATLAS Experiment at CERN. When that effort concluded, the same verification infrastructure was reused on the Global Feature EXtractor (gFEX) project. As MHRL Sàrl took on subrecipient work for the US ATLAS HL-LHC Upgrade Project, we needed those hard-won testbenches to keep working, this time on Global Trigger firmware, the electronics that select collision data for recording at the upgraded LHC. Adopting Riviera-PRO preserved that continuity: apart from a few lines of SystemVerilog which were quickly sorted out with Aldec's responsive technical support, the UVM code base migrated unchanged and now runs as automated regressions in GitLab CI. Riviera-PRO's UVM and SystemVerilog compliance and straightforward CI integration have since made it a dependable part of our verification flow. For a small engineering company contributing to a project of this scale, reusing verification IP rather than rebuilding it was a game changer."
