Aldec Customer Use Cases


Related Solutions:

Riviera-PRO™

The User:

Xelic, an OTN IP Core and Subsystem provider, required:

  • SystemVerilog-based simulation capability with:

- UVM support
- Coverage driven constrained random methodology   support
- Functional Coverage
- Code Coverage
- Assertions
- GUI interface for debug
 

  • Reasonable simulation performance
  • Vendor library support (mainly FPGA)
  • Mixed-language support for legacy VHDL/Verilog environments as well as VHDL-only (design and verification)
  • A practical licensing price point to support development (mini regressions, GUI, and batch jogs)  along with production release to include full multi-seeded batch regressions and coverage

 

How Aldec Delivered:

  • Mixed language support VHDL/Verilog
  • Pure VHDL support
  • SV/UVM support

- Constrained Randomization
- Functional Coverage
- Code Coverage
- Assertions

  • Vendor library support for Altera and Xilinx
  • Powerful GUI for development and debugging
  • Multiple levels of optimization for performance tuning
  • Responsive tech support that delivered productivity enhancing tips/techniques
  • Reasonable cost for competitive performance
  • Ease of operation with third party/in-house queue manager

 

Ask Us a Question
x
Ask Us a Question
x
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.
We use cookies to ensure we give you the best user experience and to provide you with content we believe will be of relevance to you. If you continue to use our site, you consent to our use of cookies. A detailed overview on the use of cookies and other website information is located in our Privacy Policy.