Aldec and Codasip at Embedded World: Showcasing an Integrated UVM Simulation Environment for Verifying Custom Instructions with RISC-V Cores

Date: Feb 19, 2020
Type: Release

Nuremberg, Germany – February 19, 2020 – Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, is exhibiting at Embedded World in Nuremberg, Germany on February 25-27, 2020. Aldec and Codasip will be showcasing an integrated UVM simulation environment for verifying custom instructions with RISC-V cores.


By integrating Aldec’s Riviera-PRO™ with Codasip’s Studio™, verification of custom instructions at the RTL implementation level becomes an incredibly powerful platform for RISC-V processor deployment.

  • In Studio, users can
    • describe the RISC-V architecture and add custom instructions using CodAL high level language
    • modify the pipeline
    • configure random instruction generator
    • auto-generate the HDK, SDK, RTL implementation and C++ reference model and UVM environment
    • start RTL simulation
    • setup breakpoints
    • debug
  • In Riviera-PRO, users can
    • run RTL simulation and debug applications and core architecture
    • inspect simulation waveforms
    • use the UVM Graph & Toolbox to view the graphical representation of the UVM components, objects and the transaction level modeling (TLM) connections between them giving the user an overall perspective on the testbench architecture and the dataflow
    • use code coverage to analyse the efficiency of the UVM tests for exercising various parts of the RTL implementation code


“The ability to add custom instructions to processor IPs is a remarkable advantage of the open-source RISC-V ISA,” said Louie De Luna, Aldec’s Director of Marketing. “Custom instructions lead to higher performance with less amount of code, and useful for optimizing the core for targeting specific embedded applications. We look forward to continue to work with Codasip as we address new verification challenges with RISC-V”.


“Variability of the RISC-V ISA-based processor family brings new challenges to design flow. In particular, IP and SoC verification needs productivity boost tools and seamless integration into our design environment,” said Karel Masařík, CEO of Codasip. “Our generic UVM methodology combined with Aldec's simulation and code coverage efficiency analysis helps us add the desired RISC-V core extensions and provide core customization faster than our competition.”


See the demo and talk to our experts at Aldec Booth#4-560 and Codasip Booth#3A-536 (RISC-V booth, pod 13).


About Codasip

Codasip delivers leading-edge processor IP and high-level design tools, providing ASIC designers with all the advantages of the RISC-V open ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors.


About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.

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