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Aldec’s Latest Embedded Development Platform is First to Feature Largest PolarFire and SmartFusion2 FPGAs on a Single Board

Date: Nov 26, 2019Type: Release

Aldec’s HES-MPF500-M2S150 Development Kit supports the early co-development and co-verification of hardware and software in projects targeting FPGAs from Microchip’s PolarFire and SmartFusion2 families.

 

Henderson, USA – November 26, 2019 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has launched the HES-MPF500-M2S150 Development Kit, to aid engineers in the development of FPGA-based embedded systems that will use devices from either or both of Microchip’s PolarFire or SmartFusion2 families.

 

The HES-MPF500-M2S150 Development Kit is the first of its kind in the industry to carry devices from Microchip’s PolarFire and SmartFusion2 FPGA families, whereas all other development boards available carry one or the other. In addition, such single-FPGA boards carry just mid-range devices.

 

“This latest addition to our HES product line is in direct response to requests from customers who are in need of advanced and versatile prototyping platforms that provide easy access to one or both of Microchip’s popular FPGAs,” comments Zibi Zalewski, General Manager of Aldec’s Hardware Division. “By selecting Microchip’s largest devices from both families, we are sparing engineers from worrying about optimization early on in their design flow. Instead, they can do their What If experimentation and address optimization and other performance issues once they have achieved the top-level functionality they desire.”

 

Zalewski goes on to flag that although a design might only be targeted at the PolarFire FPGA the SmartFusion2 device can be used as an embedded host and test driver. Similarly, the PolarFire FPGA can be loaded with test vectors for verifying the design on the SmartFusion2 device.

 

The HES-MPF500-M2S150 Development Kit features Microchip’s low power PolarFire MPF500T FCG1152 FPGA, which has 481k logic elements, 1480 math blocks, 33Mbits of RAM, and 584 I/Os. In addition, the PolarFire family of FPGAs afford high security, which is of great benefit in the fight against cyber-crime.

 

Also featured on the HES-MPF500-M2S150 is Microchip’s SmartFusion2 M2S150 FPGA. At the heart of this SoC device is an embedded Arm Cortex-M3 microcontroller subsystem with DDR3 memory controllers.

 

The two FPGAs on Aldec’s HES-MPF500-M2S150 are connected via direct I/Os and both devices have access, via a PCIe switch, to a PCIe x4 Gen2 Edge Connector; and it is this switch that allows the FPGAs to work together or independently.

 

High speed serial I/Os are available on both sides of the kit (i.e. for the PolarFire and SmartFusion2) via QSFP+ ports plus the SmartFusion2 can communicate with the outside world via ethernet or USB. Connection to peripherals is achieved through an FMC HPC connector with 134 I/Os and 8 high speed serial I/Os. Aldec has a growing portfolio of FMC cards that includes ones tailored for the development of ADAS, IoT, networks and high-performance computing (HPC) applications.

 

The HES-MPF500-M2S150 Development Kit is available to order now and includes designer resources, sample designs, utilities and documentation.

 

 HES-MPF500-M2S150 Development Kit HES-MPF500-M2S150 Development Kit

About HES

Aldec offers a portfolio of versatile HES™ prototyping boards based on the largest and industry leading FPGAs of the Xilinx Virtex UltraScale+, UltraScale, Virtex-7 families and Microsemi PolarFire and SmartFusion2 families. The boards are architected to allow for easy expansion using standardized FMC and BPX daughter card connectors. Thanks to HES-DVM software HES boards can be reused at earlier verification stages for simulation acceleration, emulation, hybrid co-emulation with virtual platforms and prototyping. With HES Proto-AXI software package HES boards are also used for algorithms acceleration in High Performance Computing (HPC) applications.

 

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com



Developing Robust Finite State Machines Code With Lint Tools

Date: Nov 26, 2019Type: Release

Henderson, USA – November 26, 2019 – As design size and complexity grows, the design verification effort grows even more. It takes significant amount of time to thoroughly verify complex control logic of a design, which is the key and the most critical component of design functionality. One of the most common design patterns in the control logic design are finite state machines. They could be designed in different styles, state and output logic encodings, being either complex or simple for design, maintenance and verification. It is important to use the “Design-for-Verification” approach to develop Finite State Machines in a concise, robust and easy-to-verify way.

 

RTL code linting is the well-known approach ensuring design to be compliant with the collection of industry-best design guidelines for hardware development. Moreover, linting is able to automatically extract Finite State Machines structures from the design code and reveals FSM design bugs at the earliest stages of code development.

 

Standardizing FSM design patterns is an important part of RTL code standardization and it is widely used in many chip design houses. Lint tools formally verify the code to comply to company standards, avoiding design reviews and manual code check. Lint tools checks various FSM code features such as:

 

  • State Naming conventions, including maximum name length, upper/lower case, etc.
  • Proper FSM isolation in design units (such as maximum one FSM for the design unit).
  • Proper FSM code sequencing (such FSM states declaration right after the states definition).
  • Usage of case statements in the next-state logic (avoiding “if” statements usage).
  • Usage of two or three processes to describe the FSM (avoiding the error-prone one-process FSM implementation).

Lint tools automatically identify FSM code in RTL and extract FSM structure, presenting it in the FSM graph window. Designers visually approve the FSM design intent reviewing these FSM graphs. For the legacy code, extracted FSM graphs act as a design specification, allowing better understanding of the RTL code and facilitating its reuse. The following picture demonstrates the FSM graph extracted by Lint tools:

 

After FSM extraction, Lint tools apply various structural and functional checks to further verify FSM correctness and its compliance to company standards. For example, it is a good practice to avoid using Mealy and Mixed FSM types, preferring Moore FSM types only. Moore FSM outputs are registered and therefore they don’t propagate possible FSM input glitches to FSM outputs. Moore FSM are preferable from a timing perspective too, as FSM output timing paths include output decoding logic only. Also, it is a good practice to enforce a specific state encoding type to better fit a design into design requirements. For example, the one-hot encoding with Moore FSM type is preferable for the high-speed designs, while Gray encoding being preferable for the low-power applications, etc.

For the rest of this article, please visit Semiengineering.com.

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