Event Details View All Recorded Events Date Event Type Location Action Nov 06, 2025 Boost FPGA Reliability with Advanced Linting and CDC Analysis (US) Time: 11:00 AM - 12:00 PM (PST) AbstractPresented by DesignLinx, the AMD Embedded Premier Partner of the Year for the Americas, and Aldec, the industry leader in simulation and verification solutions, this webinar will show you how to unlock the full potential of your FPGA designs with advanced static linting and CDC analysis. These powerful verification methodologies detect structural issues, eliminate hidden bugs, and ensure reliable clock-domain crossings early in the flow. As a result, you'll improve design quality, accelerate verification, and reduce costly iterations—empowering your team to deliver safer, faster, and more robust FPGA solutions. FPGA designs targeting AMD devices demand robust and efficient RTL implementation to fully leverage advanced architectures and meet performance, timing, and reliability goals. Undetected RTL coding issues can trigger costly design iterations and unpredictable failures late in the FPGA development flow, often during synthesis, implementation, or hardware bring-up. Advanced linting provides a powerful static analysis methodology tailored for RTL, detecting issues long before simulation or lab validation. By applying hundreds of design rules relevant to FPGA design—including synthesizability checks for Vivado®, clock domain crossing (CDC) analysis, and reset network integrity—linting helps designers uncover bugs, inefficiencies, and mismatches early in the process. In this webinar, we’ll demonstrate how advanced linting and CDC analysis can specifically enhance AMD FPGA projects, streamline the development process, and ensure higher design reliability. Practical examples will highlight how linting supports optimal code quality, enables design reuse, and prevents late-stage surprises during synthesis and place-and-route. Agenda: Overview of Advanced Linting in AMD FPGA Design Flows Best Practices for Effective RTL Linting Real-World Examples: Identifying functional bugs early in HDL targeting AMD FPGAs Optimizing RTL for Vivado synthesis and implementation Enhancing design quality, reuse, and timing closure reliability Detecting clock/reset tree and CDC issues unique to FPGA architectures Key Takeaways & Q&A Presenters BIO Alex Gnusin, ALINT-PRO Product Manager, AldecAlex accumulated 27 years of hands-on experience in various aspects of ASIC and FPGA design and verification. As a verification prime for a multi-million gates project in companies such as IBM, Nortel, Ericsson and Synopsys Inc, he combined various verification methods such as static linting, formal property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology. Don St. Pierre, Director, Engineering Solutions - DesignLinx Don St. Pierre is a 30-year veteran of the electronics/semiconductor industry. He founded DesignLinx in 2009 after a 15-year stint with Xilinx, Inc. While at Xilinx, Don held various positions in Applications, Hardware/System Design, Field Applications Engineering (FAE), and Professional Services Management. Don earned 9 U.S. Patents during his employment with Xilinx in San Jose and later earned the prestigious award of North American FAE of the Year (2005) – an award given to Xilinx FAEs based on outstanding customer support, account growth and development. Webinar Online Register
