Does DO-254/CTS™ Support FPGAs with Serial High-speed I/Os?

A trending question from the DO-254 community

Louie de Luna, Aldec DO-254 Program Manager
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As a DO-254 evangelist, I travel quite a bit attending conferences and meeting customers all over the world. One question I occasionally get from engineers is whether Aldec’s mil/aero verification solution, DO-254/CTS™, supports verification of FPGA designs with high speed interfaces (for example ARINC 818, LVDS, DDR3 or PCIe).

Depending where I’m at I’ll tell them, “Oui!” or “Hai!” or simply “You bet it does”. Occasionally I’ll respond, “화장실이 어디 있어요!” in hopes that someone will kindly direct me to the nearest restroom.

I’ll then go on to explain that DO-254/CTS supports verification of such high speed interfaces using LVDS links or FPGA- integrated multi-gigabit transceivers. We recently completed for one of our customers a DO-254 DAL A project using an Altera® Stratix™ IV FPGA device.  Their target FPGA had 8 asynchronous CLKs, ~650 I/Os and contains interfaces to ARINC 818 running at 1.0625GHz, LPDDR running at 533MHz and LVDS links running at 585MHz – and DO-254/CTS performed beautifully.  

To improve results validation and analysis for designs using serial high speed I/Os, the rockstars in Aldec R&D delivered our users a gift, C/C++ API. In-hardware verification results for high speed I/Os usually contain a significant amount of data and analyzing them via waveforms is a tremendous task. The use of C/C++ API enhances the capabilities of interpreting in-hardware verification results in a custom format or user-specific application.

Here’s an example. The video frames for ARINC 818 (ARINC protocol for high bandwidth, low latency, uncompressed digital video transmission in avionics systems) contain a significant amount of data and results analysis via waveforms would be a challenge. The ARINC 818 video (ADVB) frames must be compared with several possible patterns suitable for a given time. Errors should be reported if the frame does not match any available pattern. In case of errors, it is more natural to view the contents of the video frame in graphical form or automatically compare with golden patterns.  Users can create their own C/C++ functions using the API to save the video frames to AVI or BMP for visual inspection or comparison against several possible golden patterns.

For videos, white papers and other resources on DO-254/CTS and C/C++ API for results validation, check out

Louie de Luna is responsible for FPGA level in-target testing technology and requirements lifecycle management for DO-254 and other safety-critical industry standards.  He received his B.S. in Computer Engineering from University of Nevada in 2001.  His practical engineering experience includes areas in Acceleration, Emulation, Co-Verification and Prototyping, and he has held a wide range of engineering positions that include FPGA Design Engineer, Applications Engineer, Product Manager and Project Manager.

  • Products:
  • DO-254/CTS
  • FPGA Test System


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