High Performance SoC’s Pushing the Limit of Prototyping Boards

Aldec HES-7 Backplane, a Cost-Effective Solution

Bill Jason P. Tomas, Product Engineer, Hardware Division
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As newer generation FPGAs provide users higher logic capacity for system design, SoC's are concurrently  growing more complex with the integration of high speed serial protocols, multi-core processors, and media interfaces. These SoC designs are pushing the limits of FPGA utilization, and growing up to the multi-million ASIC gate count, which itself is steadily increasing.



Design teams need to be able to provide enough “wiggle room” in their off-the-shelf prototyping boards to be able to reuse HDL for future projects and expansion to keep up with the growing trend. This puts designers into a bind, since they need to purchase a prototyping board which can handle their current design, while providing them enough capacity to grow in the future. This may not be an issue for larger companies who have the appropriate resources to build their own development platforms or purchase costly off-the-shelf board, but for many companies it is.


HES_BP_img_02The Aldec HES-7 backplane has four expansion slots, each capable of housing a single HES-7 board with up to 24M ASIC gates. This allows designers to create designs using a single prototyping platform, and expand capacity only when needed. This can greatly reduce project cost since companies need only purchase the logic capacity they require.



At the 2013 Design Automation Conference (DAC), Aldec will provide an overview of the backplane board, discuss the advantages of the HES-7 scalability, and how it is even possible to serially daisy chain two backplane boards together for up to 144M ASIC gates.

Bill is responsible for Aldec Hardware Emulation and SoC / ASIC Prototyping. He received his B.S. in Computer Engineering from Auburn University in Alabama in 2011, and currently undertaking his M.S in Electrical Engineering with a focus on hardware emulation methodology and Built-In-Self-Test for high capacity FPGAs. He is also currently a graduate research assistant for the University of Nevada Systems and Integration laboratory studying Network-on-Chip BIST strategies. 

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