Active-HDL Tool Trainings Help Engineers Get up to Speed Quickly

Workshop Training Books Available for Purchase

Satyam Jani, Product Manager Software Division
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In today's competitive atmosphere, the ability to get up to speed with any tool is critical. Over the years, Aldec has conducted numerous trainings to help engineers increase their productivity by enhancing their knowledge of Active-HDL, Aldec’s FPGA design entry and simulation tool.

 

Based on feedback, we have learned that engineers have found the comprehensive material that accompanies these trainings to be immensely useful, both during class as well as for ongoing reference. ‘FPGA Design and Verification – Using Active-HDL’ contains a complete Workshop Notebook and accompanying Lab Book, and is now available for separate purchase without onsite training for those who would like to learn more about Active-HDL at their own pace. Complete sets are available for purchase at the cost of $89 USD plus shipping. Learn more.

 

The Active-HDL Workshop Notebook and Lab Book are an integral part of Aldec’s tool training program. This training material is designed with an objective to increase user productivity significantly by preparing them on how to use Active-HDL most effectively. The style of this training material is a blend of traditional classroom teaching with hands-on lab covering real-time design situation. This concept-to-project training material is aimed for current users of Active-HDL only and covers wide variety of topics from design entry, simulation and debugging.

 

This material covers the following topics in detail:

  • Project Management
  • Design Entry Tools Basic – HDL Editor, BDE and FSM
  • Design Entry Tools Advanced – HDL Editor, BDE and FSM
  • Running Simulation
  • Waveform Viewer
  • Code Coverage
  • Design Rule Checking
  • Documentation – HTML and PDF

To order workbook materials or to learn more, please visit www.aldec.com/support/training/workbooks.

 

To host an onsite methodology training or tool training course at your own location, please contact training@aldec.com.

Satyam manages Aldec’s leading FPGA design entry and simulation tool – Active-HDL. He received his B.S. in Electronics Engineering from Sardar Patel University, India in 2003 and M.S in Electrical Engineering from NJIT, New Jersey in 2005.  His practical engineering experience includes areas in Solid state electronics, Digital Designing and functional verification. He has worked in wide range of engineering positions that include FPGA Design Engineer, Applications Engineer and Product Manager.

  • Products:
  • Active-HDL
  • FPGA Design Simulation

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