Shaping the Future of ASIC/FPGA DSP Design Flow

Take our survey

Mariusz Grabowski, FPGA Design and Verification Engineer
Like(0)  Comments  (0)

Aldec is conducting a brief survey through April 30, 2013, to better address the challenges and requirements faced by DSP designers in the field.
As a thank you, a random drawing will be held among survey participants to receive a $100 Amazon giftcard.

Survey has ended.

Winner to be notified by email.

Mariusz Grabowski is an FPGA Design and Verification Engineer at Aldec. He works in the field of verification for DO-254 compliance as well as developing digital processing systems. He is proficient in digital design and verification, using hardware description languages such as Verilog/SystemVerilog and VHDL, and the use of verification methodologies such as UVM.

Mariusz is a student at the AGH University of Science and Technology in Krakow, Poland. He also gains practical experience in the AVADER Scientific Group (where he designs novel vision systems on FPGAs) and in the Integra Scientific Group (where he acquires knowledge about microprocessor systems and electronics).

  • Products:
  • Riviera-PRO
  • Advanced Verification

Comments

Ask Us a Question
x
Ask Us a Question
x
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.
We use cookies to ensure we give you the best user experience and to provide you with content we believe will be of relevance to you. If you continue to use our site, you consent to our use of cookies. A detailed overview on the use of cookies and other website information is located in our Privacy Policy.