Partition your Design for FPGA Prototyping

Easily create partitions with HES-DVM

Henry Chan, Applications Engineer
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Modern ASIC and SoC designs have increased in complexity such that multiple FPGAs of the largest capacity are now required to prototype the entire functionality of the design. As design sizes increase, more and more FPGAs are required. The capacity and pin limitations of FPGAs create constraints for how the ASIC/SoC design can be mapped into the FPGAs. Aldec’s HES-DVM's prototyping mode accounts for the limitations of the target FPGAs and allows the user to map a design to the FPGAs within these constraints.


Partitioning a design to fit into multiple FPGAs can be a lot of work


Designing the partitions with HES-DVM is as easy as selecting specific VHDL/SystemVerilog design modules from the hierarchy and moving them to a desired partition. All information about the design modules and the amount of LUTs, Flip-flops, memory blocks, DSP slices, and I/O consumed are displayed for convenience. These values can also be viewed as a percentage of the target FPGAs’ available resources allowing you to know when an FPGA is full.


Adding a module to a partition


Mapping a partition to an FPGA


Once the partitions are finalized, each partition can be assigned to a specific FPGA. A design successfully fitting into the FPGAs on the target prototyping board is only the beginning. There still remains a big problem with the sheer number of connections between the partitions. Modern designs have thousands of internal signals interconnecting major blocks or sub-systems. It’s likely that there won’t be a sufficient amount of direct connections between FPGAs to support the design’s internal wiring. How can the large amount of internal design signals possibly be accommodated by the relatively smaller amount of I/O available from the FPGAs?


Fear not. Aldec’s HES-DVM has accounted for this and provides you with the ability to create Inter-Chip Connectors (ICC). These ICCs can take your design’s significant amount of internal signals and funnel the values out to the FPGA’s available physical pins. This technique allows the limited number of pins on the FPGA to provide a sufficient bridge for the vast internal connections of your design. The ICC also allows these design signals (logical connections) to travel between FPGAs using the differential or single-ended I/O of the FPGA.


 Inter-Chip Connector dialog box


With all the headaches associated with prototype bring-up, why not manage your partitioning decisions with software? HES-DVM’s prototyping mode will allow you to easily design your partitions according to the resource constraints from your target FPGAs and help to manage connections between them. This allows you to get your prototype up and running on multi-FPGA boards quickly and easily.


For more information on Aldec’s HES-DVM and its muti-FPGA design partitioning capabilities, you can visit: or contact us at

As an Aldec Applications Engineer, Henry has intimate knowledge of the inner workings behind the latest verification tools, languages, and methodologies. He has a wide breadth of experience across various areas including simulation, emulation, and embedded systems. Henry received his B.S. in Computer Engineering from the University of Nevada, Las Vegas.


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