No doubt you’ve heard Python is making inroads in the EDA landscape, but is all the hype justified? Do the productivity benefits of a dynamic language translate to gains for real-world development for ASIC and FPGA designs? Chris Higgs of Potential Ventures will join Aldec at DAC to share his experiences using Python and Aldec Riviera-PRO to take products from idea to production quickly. We’ll explore how Python and Cocotb together create a powerful development and verification environment for VHDL and Verilog/SystemVerilog designs and cover rapid creation of testbenches and re-using existing C/C++ code in simulation, as well as advanced topics such as simulation-in-the-loop, interactive debug tools and reusing code between simulation and hardware environments. Design Automation Conference (DAC 2015) Moscone Center, San Francisco, CA June 7-11, 2015 | BOOTH #1725 Additional Aldec Sessions at DAC include Efficient Structural CDC Analysis, UVM Simulation Acceleration, High Level Synthesis with NEC, OSVVM with Synthworks, and more. Visit http://www.aldec.com/dac2015 to register for a session of your choice, and be sure to join us Monday night at DAC from 5-6pm for cocktails at Booth #1725. Putting the “Automation” back into EDA Book a slot at the Aldec booth so we can share with you our vision of what "good" could look like. Aldec is a global industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. +1.702.990.4400 sales@aldec.com www.aldec.com Don't want to receive email Updates? Unsubscribe here.
