No doubt you’ve heard Python is making inroads in the EDA landscape, but is all the hype justified?

Do the productivity benefits of a dynamic language translate to gains for real-world development for ASIC and FPGA designs? Chris Higgs of Potential Ventures will join Aldec at DAC to share his experiences using Python and Aldec Riviera-PRO to take products from idea to production quickly. We’ll explore how Python and Cocotb together create a powerful development and verification environment for VHDL and Verilog/SystemVerilog designs and cover rapid creation of testbenches and re-using existing C/C++ code in simulation, as well as advanced topics such as simulation-in-the-loop, interactive debug tools and reusing code between simulation and hardware environments.