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Date Event Type 場所 Action
Oct 26, 2017 Design Rule Checking (DRC) for Common SystemVerilog Design Mistakes (US)

Time: 11:00 AM - 12:00 PM PDT


Due to the size and complexity of current hardware designs, the design verification task has become increasingly complex and lengthy. Today, the goal is to clean up the design code as much as possible prior to entering the design verification stage. Such design code cleanup, performed during relatively short time, may significantly reduce overall design verification time and effort. As Systemverilog design constructs gain popularity among hardware designers, it is increasingly important to assist designers with Systemverilog design code verification and cleanup.

ALINT-PRO™ is a design verification solution for Systemverilog, Verilog and VHDL RTL that is able to statically verify and cleanup the code far beyond compiler-level checks. It is capable of statically verifying most of the popular Systemverilog design constructs, uncovering some of the critical design issues early in the design cycle.



  • Design Verification Challenge: The Overview
  • Problem: Low quality Systemverilog design code for  Design Verification
  • Solution: Static Code Verification prior to Dynamic one
  • ALINT-PRO Systemverilog code checks: The overview
  • ALINT-PRO place in overall Design Verification process
  • ALINT-PRO Systemverilog Plugin Live demo
  • Conclusion
  • Q&A

Presenter Bio:

Alexander Gnusin is a Verification Methodology Specialist at Aldec. Alexander Gnusin has 22 years of hands-on Design and Verification experience gained from well-known design houses - Motorola Semiconductors, IBM, Nortel Networks and Ericsson. As Verification Prime for multi-million gates project, he combined various verification methods - LINT, Formal Property checking, dynamic simulation and hardware-assisted acceleration to efficiently achieve design verification goals. He received his M.S. in Electronics from Technion, Israel Institute of Technology.

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