Play Webinar

Title: Verifying AXI Interconnects with ALINT-PRO and Riviera-PRO

Description: AXI has become the most popular internal bus protocol with today’s FPGA and SoC FPGA designs. ALINT-PRO enables FPGA designers to extract, review and statically verify AXI bus interfaces. In addition, ALINT-PRO can assist with automatic generation of test harnesses for dynamic verification. For dynamic verification of AXI interconnects, Aldec provides FPGA vendor-agnostic AXI Bus Functional Models (BFM) as well as Riviera-PRO functional verification platform. In this webinar, we will present AXI bus interface extraction and static verification with ALINT-PRO. Then, we will show how ALINT-PRO assists in test harness wrapper generation for dynamic verification with Riviera-PRO. Finally, we will show the usage of Aldec AXI BFM solution for dynamic interconnect verification.

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