Play Webinar

Title: Introduction to Logic Simulator Programming Interfaces for FPGA Designs (Part 1) The Power of Verilog’s PLI & VPI

Description: The programming interfaces of logic simulators are largely the domain of specialists writing proprietary tools and extensions and are only vaguely in the consciousness of many design and verification engineers, if aware at all. Yet the simplest use of such interfaces opens up a whole world of possibilities in extending what is achievable in verifying logic IP and with the potential for logic and embedded software co-development. The Programming Language Interface (PLI/VPI) is part of the IEEE Standard for SystemVerilog Language Reference Manual. In this part 1 of the webinar series, we will introduce the Verilog PLI and VPI and discuss the first steps of crossing from the logic domain to the software domain. We will show various working examples with memory models and virtual processors, sufficient to allow engineers to start creating their own solutions. The real-world examples will be demonstrated to show just what is possible with using these basic logic interface features that are already available, and well supported, in the Aldec simulation tools.


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