Play WebinarTitle: Using OVL for Assertion-Based Verification of Verilog and VHDL DesignsDescription: Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The OVL checkers could be used not only in dynamic simulation, but also in formal verification and emulation. Also, the OVL-based verification technology provides the easiest way for designers to implement assertion-based verification of their design. Finally, OVL supports any HDL language (Verilog, SystemVerilog, VHDL), enabling assertion-based verification with any simulation tools. In this webinar, we will present practical guidance on how to start using Open Verification Library (OVL) in design and verification process. We will provide various code examples to demonstrate how to efficiently use OVL for Verilog and VHDL design verification. Static formal and emulation-based verification methods using OVL will be outlined as well. Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
