Play WebinarTitle: UVM for FPGAs (Part 3): Verifying Zynq MPSoC Designs? Learn how UVM Register Access Layer (RAL) can helpDescription: The use of highly configurable IP-based designs have become the norm in the SoC era. Modern SoC designs targeting Xilinx® Zynq Ultrascale+ MPSoC include an extensive list of standard embedded IPs and custom IPs with memory-mapped registers. While these IPs vary in size and complexity, they are all configurable via registers that are typically composed of a field name, field width, access type, default values and policies. RTL simulations for verifying these IPs especially in various configurations require the use of hierarchical register models - creating them is not a trivial task and require a common framework and automation.Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
