Play Webinar

Title: Verification Methodology for Large-Scale FPGA designs

Description: Nowadays, Large-scale FPGA designs are comparable with ASIC designs in terms of size and complexity. However, ASIC-specific verification methodology such as SystemVerilog UVM may be still too time-consuming and impractical in FPGA world, as UVM testbenches development requires deep OOP practical knowledge and significant amount of project resources. There is a need in more lightweight but still efficient verification methodology that considers the specifics of FPGA development process. Current Webinar outlines the Verification Methodology flow for the Large-Scale FPGA designs. This methodology includes Verification planning, testbench and verification components and tests development, functional coverage collection and scripting support development for running tests and regressions. The methodology is based on Verilog and SystemVerilog languages ; it is well-suited for the FPGA designers as it does not require HVL and object-oriented specific knowledge and experience.

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