Play Webinar

Title: Verification Methodology for Large-Scale FPGA designs

Description: Nowadays, Large-scale FPGA designs are comparable with ASIC designs in terms of size and complexity. However, ASIC-specific verification methodology such as SystemVerilog UVM may be still too time-consuming and impractical in FPGA world, as UVM testbenches development requires deep OOP practical knowledge and significant amount of project resources. There is a need in more lightweight but still efficient verification methodology that considers the specifics of FPGA development process. Current Webinar outlines the Verification Methodology flow for the Large-Scale FPGA designs. This methodology includes Verification planning, testbench and verification components and tests development, functional coverage collection and scripting support development for running tests and regressions. The methodology is based on Verilog and SystemVerilog languages ; it is well-suited for the FPGA designers as it does not require HVL and object-oriented specific knowledge and experience.

Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours.

If you already have an Aldec account, please Sign In below to download the file.

Ask Us a Question
Ask Us a Question
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.