Play WebinarTitle: From OSVVM VHDL Functional Coverage to UCIS-based DatabaseDescription: In the latest release of Open-Source VHDL Verification Methodology (OSVVM), you'll find an API that allows OSVVM Functional Coverage to be recorded within a simulator. Aldec pioneered this interface and has integrated it within their simulators. OSVVM currently provides VHDL testbenches with Functional Coverage, Intelligent Coverage, and constrained random testing methods. Using this interface brings SystemVerilog like Metric Driven test capability to VHDL. OSVVM architect and VHDL trainer, JIm Lewis, together with Aldec Software Product Manager, Radek Nawrot, will demonstrate how to add this capability to your VHDL testbench.Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
