Play Webinar

Title: From OSVVM VHDL Functional Coverage to UCIS-based Database

Description: In the latest release of Open-Source VHDL Verification Methodology (OSVVM), you'll find an API that allows OSVVM Functional Coverage to be recorded within a simulator. Aldec pioneered this interface and has integrated it within their simulators.
OSVVM currently provides VHDL testbenches with Functional Coverage, Intelligent Coverage, and constrained random testing methods. Using this interface brings SystemVerilog like Metric Driven test capability to VHDL.
OSVVM architect and VHDL trainer, JIm Lewis, together with Aldec Software Product Manager, Radek Nawrot, will demonstrate how to add this capability to your VHDL testbench.


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