Play Webinar

Title: OSVVM: Advanced Verification for VHDL with Synthworks

Description: Presented by Jim Lewis, SynthWorks VHDL Training Expert, IEEE 1076 Working Group Chair, and OSVVM. OSVVM provides functional coverage and randomization utilities that layer on top of your transaction level modeling based VHDL testbench. Using these you can create either basic Constrained Random tests or more advanced Intelligent Coverage based Random tests. This simplified approach allows you to utilize advanced randomization techniques when you need them and easily mix advanced randomization techniques with directed, algorithmic, and file-based test generation techniques. Best of all, OSVVM is free and works in all of Aldec VHDL simulators.


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