VIP/IP Products

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Category: Type Part Provider Action
Peripherals and InterfacesVIP

1-Wire   

Aldec 1-Wire Slave transactor provides capability to communicate over 1-Wire bus. It consist of fully synthesizable hardware part written in Verilog and software part written in C and SystemVerilog with API in SystemVerilog. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI)

Aldec
Peripherals and InterfacesVIP

AHB (Function-based)   

Aldec AMBA High-performance Bus (AHB) transactor provides communication and monitoring capabilities with AHB devices (master and slave). It consist of fully synthesizable hardware part written in SystemVerilog and testbench part written in C++ with SystemVerilog API. Hardware and testbench parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using function based message passing (DPI)

Aldec
Peripherals and InterfacesVIP

AHB (Macro-based)   

Aldec AMBA High-performance Bus (AHB) transactor provides communication and monitoring capabilities with AHB devices (master and slave). It consist of fully synthesizable hardware part written in VHDL and software part written in C++ with API in C. Hardware and software parts communicate through the Standard Co-Emulation Modeling Interface (SCE-MI) using macro based message passing use model

Aldec
Peripherals and InterfacesVIP

AXI (Function-based)   

Aldec AMBA Advanced eXtensible Interface (AXI) transactor provides communication and monitoring capabilities with AXI devices (master and slave). It consist of fully synthesizable hardware part written in SystemVerilog and testbench part written in C++ with SystemVerilog API. Hardware and testbench parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using function based message passing (DPI)

Aldec
Peripherals and InterfacesVIP

AXI (Macro-based)   

Aldec AMBA Advanced eXtensible Interface (AXI) transactor provides communication and monitoring capabilities with AXI devices (master and slave). It consist of fully synthesizable hardware part written in VHDL and software part written in C++ with API in C. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using macro based message passing use model

Aldec
Peripherals and InterfacesVIP

CSIX   

CSIX-L1 is a Common Switch Interface, for transferring information between switching fabric and traffic
managers (network processors).
The Aldec CSIX transactor provides capability to communicate over CSIX networking interface.
It consists of:
- fully synthesizable hardware part written in Verilog
- software part written in C and SystemVerilog
- Low Level API in SystemVerilog (giving full control, e.g. of flow control)
- High Level API in SytemVerilog (taking care of flow control)
Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI)

Aldec
Peripherals and InterfacesVIP

Ethernet   

The Aldec Ethernet transactor provides capability to communicate over Ethernet networking interfaces:
- 1000 Mb/s (Gigabit Ethernet)
- 100 Mb/s (Fast Ethernet)
- 10 Mb/s
It consists of:
- fully synthesizable hardware part written in Verilog
- software part written in C and SystemVerilog
- API in SystemVerilog
Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI)

Aldec
Peripherals and InterfacesVIP

Ethernet Speed Adapter   

The Aldec Ethernet speed adapter provides capability to connect real-speed (up to 1000 Mbit/s) Ethernet interface to Ethernet DUT in Aldec emulator. Speed adapter handles synchronization between two domains (fast/real and slow/emulator) and manages protocol-specific flow control.

Aldec
Peripherals and InterfacesVIP

I2C   

Aldec Inter-Integrated circuit (I 2C)  transactor provides capability to communicate over I 2C bus. It consist of fully synthesizable hardware part written in VHDL and software part written in C++ with API in C. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using macro based message passing use model

Aldec
Peripherals and InterfacesVIP

I2S   

Aldec Inter-IC Sound (I2S) transactor provides capability to communicate over I2S bus. The I2S transactor uses one channel but combines both transmitter and receiver functions. Communication between an HDL model with a C model is provided by Standard Co-Emulation Modelling Interface (SCE-MI)

Aldec
Peripherals and InterfacesVIP

JTAG   

Aldec IEEE 1 149.1 Standard Test Access Port and Boundary-Scan Architecture (Joint Test Action Group JTAG )  transactor provides capability to communicate over JTAG interface. It consist of fully synthesizable hardware part written in VHDL and software part written in C++ with API in C. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using macro based message passing use model

Aldec
Peripherals and InterfacesVIP

JTAG - Tensilica OCD   

Aldec Tensilica JTAG transactor provides capability to connect software debugger (e.g. gdb or eclipse-based) to Tensilica CPU, without physical JTAG cable. It consist of fully synthesizable hardware part written in SystemVerilog and software library for Tensilica XOCD. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using function based message passing (DPI)

Aldec
Peripherals and InterfacesVIP

OCP   

Aldec OCP (Open Core Protocol) version 2.1 provides capability to communicate over OCP bus as master and slave. It consists of fully synthesizable hardware part written in VHDL and software part written in C++ with API in C. Communication between HDL and C model is provided by Standard-CoEmulation Modelling Interface (SCE-MI)

Aldec
Peripherals and InterfacesVIP

PCIe   

Aldec PCI Express transactor provides communication capabilities with PCIe devices. It consist of fully synthesizable hardware part written in SystemVerilog and testbench part written in C++ with SystemVerilog API. Hardware and testbench parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using function based message passing (DPI).

Aldec
Peripherals and InterfacesVIP

PCIe Speed Adapter   

The Aldec PCI Express speed adapter provides capability to connect real-speed PCIE device to PCIe DUT in Aldec emulator. Speed adapter handles synchronization between two domains (fast/real and slow/emulator) and manages protocol-specific flow control.

Aldec
Peripherals and InterfacesVIP

SPI42   

ALDEC SPI 4.2 transactor provides communication with Link Layers devices with SPI 4.2 interface. It consist of fully synthesizable hardware part written in SystemVerilog and testbench part written in C++ with SystemVerilog API. Hardware and testbench parts communicate through the Standard CoEmulation Modelling Interface (SCE-MI) using function based message passing (DPI)

Aldec
Peripherals and InterfacesVIP

TLM2SCEMI_AHB   

Aldec TLM2SCEMI_AHB gives ability to connect Virtual Platform with AMBA AHB-based SoC in emulator. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using macro based message passing use model

Aldec
Peripherals and InterfacesVIP

TLM2SCEMI_AXI   

Aldec TLM2SCEMI_AXI gives ability to connect Virtual Platform with AMBA AXI-based SoC in emulator. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using macro based message passing use model

Aldec
Peripherals and InterfacesVIP

UART   

Aldec UART transactor provides capability for serial communication with devices like CPU. It consists of fully synthesizable hardware part written in VHDL and software part written in C++ with API in C. Communication between HDL and C model is provided by Standard Co-Emulation Modelling Interface (SCE-MI)

Aldec
Peripherals and InterfacesVIP

USB 2.0   

Aldec Universal Serial Bus device transactor provides capability to communicate over USB2.0 bus. It consist of fully synthesizable hardware part written in SystemVerilog and software part written in C++ with C API. Hardware and software parts communicate through the Standard Co-Emulation Modelling Interface (SCE-MI) using macro based message passing

Aldec
Peripherals and InterfacesVIP

USB Speed Adapter   

The Aldec USB speed adapter provides capability to connect real-speed USB device to USB DUT in Aldec emulator. Speed adapter handles synchronization between two domains (fast/real and slow/emulator) and manages protocol-specific flow control.

Aldec
Peripherals and InterfacesVIP

Wishbone   

Aldec WISHBONE Master Transactor provides capability to communicate over WISHBONE bus in Classic Mode. It consists of fully synthesizable hardware part written in VHDL and software part written in C++ with API in C. Communication between HDL and C model is provided by Standard Co-Emulation Modelling Interface (SCE-MI)

Aldec
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