Active-HDL EDU Configurations Collapse All Descriptions Expand All Descriptions Show All Editions Features EDU Edition[Hide] Design Entry and DocumentationExport to PDF/HTML/Bitmap GraphicsThe ability to quickly document designed components is becoming critical with the increased complexity of designs, ubiquitous IP re-use, and design teams scattered across many floors, departments, or countries. More HDL, Text, Block Diagram and State Machine EditorWith Active-HDL, you can mix different types of descriptions. Your design can include textual HDL code as well as block diagrams and state diagrams. More Code2GraphicsCode2Graphics More Code Generation ToolsIP Core Component GeneratorThe IP CORE Generator is a tool built-into Active-HDL that comes with a rich set of parameterized modules. They are ready-to-use in any VHDL- or Verilog-based system. More Testbench Generation from Waveforms Powerful testbench generation automation features have been provided to speed functional verification. A testbench for any design unit can be generated from waveforms created in the waveform editor or during a simulation run. More Project ManagementDesign Flow Manager for All FPGA VendorsThe Design Flow Manager configures, constrains and executes simulation, synthesis and implementation tools for all devices from Altera®, Atmel®, Lattice®, Microsemi™ (Actel), Quicklogic®, Xilinx® and more in one integrated development environment. More Support for Multi-Design WorkspaceDesigners can open multiple Active-HDL designs simultaneously and integrate them into one super-project. More Supported StandardsVHDL IEEE 1076 (1987, 1993, 2002 and 2008)ALDEC simulators provide full support of the IEEE 1076-1993 Standard, IEEE 1076™-2002 VHDL standard and majority of just published IEEE 1076™-2008 Standard. More Note (1) and (2)Verilog® HDL IEEE 1364 (1995, 2001 and 2005)ALDEC simulators provide full support of the IEEE 1364-2005 Standard. To enable simulation of a large variety of Verilog designs, both legacy and new, ALDEC simulators can be set to work in Verilog ’95, 2001 and 2005 modes. More Note (1) and (2)SystemC™ 2.3.1 IEEE 1666™/TLM 2.0SystemC is a C library that extends C to enable hardware modeling. Although strictly a C class library, SystemC is sometimes viewed as being a language in its own right More Note (1) and (2)SystemVerilog IEEE 1800-2012 (Design)SystemVerilog is a set of extensions to the Verilog HDL that allow higher level of modeling and efficient verification of large digital systems. More Note (1) and (2)EDIF 2 0 0Simulation of netlist in EDIF 2 0 0 format is supported by most Aldec Simulators. More Note (1) and (2)Simulation/VerificationVerilog Programming Language Interface (PLI/VPI)The Verilog PLI (Programming Language Interface) and VPI (Verilog Procedural Interface) provide a standard mechanism to access and modify data in a simulated Verilog model. More Debug and AnalysisAccelerated Waveform ViewerAccelerated Waveform Viewer More Language Assistant with Templates and Auto-completeLanguage Assistant with Templates and Auto-complete More Co-Simulation InterfacesMathWorks MATLAB®Aldec simulators integrate The MathWorks' intuitive MATLAB language and a technical computing environment. More LicensingNode Locked or Floating LicenseNode Locked License More One Year Time Based LicenseOne Year Time Based License (TBL) grants a designer a license to use the product for a period of one year. A 1 year support contract is included with the purchase of TBL license. More Supported PlatformsWindows® 8.1/8/7/Vista/2012/2008/2003 - (32-Bit)Builds are tested on all the latest platforms, including Windows 8, to ensure correct operation on users' workstations. More Note (1) and (2) - Simulation performance limitations compared to full commercial release of Active-HDL: Performance Restrictions: 4x slow downCapacity Restrictions: 20,000 instances - 20x slow down. Sign In Username: Password: Forgot your password? Sign In Close Ask Us a Question x Ask Us a Question x Name: Phone: Email: Question: Security code: Incorrect data entered. Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question. Internal error occurred. Your question was not submitted. Please contact us using Feedback form.