Active-HDL EDU Configurations

Features EDU Edition[Hide]
Design Entry and Documentation
Export to PDF/HTML/Bitmap Graphics
The ability to quickly document designed components is becoming critical with the increased complexity of designs, ubiquitous IP re-use, and design teams scattered across many floors, departments, or countries. More   
HDL, Text, Block Diagram and State Machine Editor
With Active-HDL, you can mix different types of descriptions. Your design can include textual HDL code as well as block diagrams and state diagrams. More   
Code2Graphics More   
Code Generation Tools
IP Core Component Generator
The IP CORE Generator is a tool built-into Active-HDL that comes with a rich set of parameterized modules. They are ready-to-use in any VHDL- or Verilog-based system. More   
Testbench Generation from Waveforms
Powerful testbench generation automation features have been provided to speed functional verification. A testbench for any design unit can be generated from waveforms created in the waveform editor or during a simulation run. More   
Project Management
Design Flow Manager for All FPGA Vendors
The Design Flow Manager configures, constrains and executes simulation, synthesis and implementation tools for all devices from Altera®, Atmel®, Lattice®, Microsemi™ (Actel), Quicklogic®, Xilinx® and more in one integrated development environment. More   
Support for Multi-Design Workspace
Designers can open multiple Active-HDL designs simultaneously and integrate them into one super-project. More   
Supported Standards
VHDL IEEE 1076 (1993, 2002, 2008 and 2019)
ALDEC simulators provide comprehensive support of the IEEE 1076-1993 Standard, IEEE 1076™-2002 VHDL standard and majority of just published IEEE 1076™-2008 Standard. More   
Note (1) and (2)
Verilog® HDL IEEE 1364 (1995, 2001 and 2005)
ALDEC simulators provide full support of the IEEE 1364-2005 Standard. To enable simulation of a large variety of Verilog designs, both legacy and new, ALDEC simulators can be set to work in Verilog ’95, 2001 and 2005 modes. More   
Note (1) and (2)
SystemC™ 2.3.1 IEEE 1666™/TLM 2.0
SystemC is a C library that extends C to enable hardware modeling. Although strictly a C class library, SystemC is sometimes viewed as being a language in its own right More   
Note (1) and (2)
SystemVerilog IEEE 1800 - 2012 (Design)
SystemVerilog is a set of extensions to the Verilog HDL that allow higher level of modeling and efficient verification of large digital systems. More   
Note (1) and (2)
EDIF 2 0 0
Simulation of netlist in EDIF 2 0 0 format is supported by most Aldec Simulators. More   
Note (1) and (2)
Verilog Programming Language Interface (PLI/VPI)
The Verilog PLI (Programming Language Interface) and VPI (Verilog Procedural Interface) provide a standard mechanism to access and modify data in a simulated Verilog model. More   
Debug and Analysis
Accelerated Waveform Viewer (ASDB)
Accelerated Waveform Viewer (ASDB) More   
Language Assistant with Templates and Auto-complete
Language Assistant with Templates and Auto-complete More   
Co-Simulation Interfaces
MathWorks MATLAB®
Aldec simulators integrate The MathWorks' intuitive MATLAB language and a technical computing environment. More   
Node Locked or Floating License
Node Locked License More   
One Year Time Based License
One Year Time Based License (TBL) grants a designer a license to use the product for a period of one year. A 1 year support contract is included with the purchase of TBL license. More   
Supported Platforms
Windows® 8.1/8/7/Vista/2012/2008/2003 - (32-Bit)
Builds are tested on all the latest platforms, including Windows 8, to ensure correct operation on users' workstations. More   
Note (1) and (2) - Simulation performance limitations compared to full commercial release of Active-HDL:
Performance Restrictions: 4x slow down
Capacity Restrictions: 20,000 instances - 20x slow down.
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