HDL, Text, Block Diagram and State Machine Editor

Category : Design Entry and Documentation

With Active-HDL, you can mix different types of descriptions. Your design can include textual HDL code as well as block diagrams and state diagrams.

HDL Editor - non-formatting text editor that includes a language assistant with a set of VHDL, Verilog, SystemC, and SystemVerilog language templates, keyword, color coding, type-ahead auto-completion, hyperlinked language reference manuals and multi-window workspace.

State Diagram Editor - a tool for creating complex, hierarchical FSM diagrams, which can be automatically converted into the corresponding HDL source code and testbench.

Block Diagram Editor - a tool for graphical (schematic) design entry. If your HDL design is in large part structural, it may be easier for you to enter its description graphically as a block diagram, rather than typing hundreds of source code lines. The Block Diagram Editor will then convert the diagram automatically into structural VHDL, Verilog or EDIF netlist. Block Diagram Editor comes with pre-loaded primitive symbol libraries from most FPGA vendors.

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