Event Details

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Date Event Type Location Action
Oct 18, 2018 Verifying Finite State Machines with Aldec Products (EU)

Time: 3:00 PM – 4:00 PM (CEST)



Finite State Machines play a key role in design functionality being an essential part of design control logic. FSM-related bugs have direct influence on core design functionality, and usually there are no workaround solutions to the FSM-related issues.  Therefore, de signers have to pay special attention to the correct design and verification of the FSM code.


Static FSM verification methods complement functional simulation to achieve flawless FSM functionality. Static code styles and naming conventions checks help designers to develop clear and concise FSM code as well as enforce the company-specific FSM development styles and restrictions. The recently added FSM viewer allows designers to extract and explore FSM structures in existing RTL code for the debugging, back-annotation and documentation purposes.




  • The key role of Finite State Machines verification in design safety
  • Finite State Machine overview and definitions
  • Static Finite State Machines verification types
  • FSM extraction and exploration with ALINT-PRO
  • ALINT-PRO FSM verification demo
  • Conclusion
  • Q&A


Presenter Bio:

Alexander Gnusin, Design Verification Technologist. Alexander Gnusin has accumulated 22 years of hands-on experience in various aspects of ASIC and FPGA design verification. He has worked with IBM, Nortel and Synopsys Inc.

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