Webinar Replay – Insight into Creating a Common Testbench

Date: Jun 10, 2020
Type: In the News

Henderson, Nevada, USA – June 10th, 2020 These days the verification process starts right when the design process begins, and it keeps going well past the end of the design phase. Simulation is used extensively at every stage of design and can go a long way to help validate a design. However, for many types of designs, especially those that process complex data streams, emulation has to be used to ensure proper operation. In a recent webinar Aldec not only discusses the limitations of simulation-only verification for ASICs and large FPGAs, they also help show how it is possible to create common testbenches that are applicable to emulation as well to improve efficiency and help in problem diagnosis.


In the webinar titled Common Testbench Development for Simulation and Prototyping, Alexander Gnusin goes into great detail about the reasons for using a common testbench between simulation and emulation, and then he dives into the specifics of how to make it happen.


Given the relatively slow speed of simulation, emulation is the only way to run enough cycles to ensure that large designs operate properly with large frame sizes. Similarly, simulation time increases as more of the system is included in the scope. Real hardware environments also differ from simulations, so it is important to factor this in as well. Lastly, as reliable as synthesis and STA are, it is imperative to simulate at the gate level to ensure the hardware implementation is correct.


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