Aldec @ DAC 2018: Presenting Innovative SoC Design & Verification Methodologies

Date: Jun 7, 2018
Type: Release

Henderson, NV – June 7, 2018 – Aldec, Inc. a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for ASIC and FPGA designs, once again innovates and delivers free technical sessions at the Design Automation Conference (DAC) in San Francisco, California. 


“This is our 34th year at DAC, and we are excited to present our latest breakthrough innovations in SoC Design & Verification at DAC,” said Louie De Luna, Aldec Director of Marketing. “Together with our product and technology experts, we will cover verification methodologies in the areas of Emulation and Prototyping, Mixed-Signal Simulation, Machine Learning and High-Performance Computing, Static Design Verification, VHDL 2018, Embedded Vision for Automotive and Safety-Critical Verification Best Practices.”


Technical Sessions and Demos

June 25-27, 2018 from 10:00 AM to 6:00 PM @ Booth #2628

Register Now 

The following presentations will be offered continuously at the Aldec booth throughout the day. Don’t forget to visit our coffee bar while you’re there!


Presentation Track 01: Single Platform for ASIC/SoC Emulation and Prototyping Read more

Presentation Track 02: Mixed-Signal and Mixed-Language Simulation Solutions Read more

Presentation Track 03: Static Design Verification Methodologies Read more

Presentation Track 04: Machine Learning, High Performance Computing & Embedded Vision Read more

Presentation Track 05: Traceability and Reusability for Safety Critical Projects Read more


Contact or call +1(702)990-4400 for more details.


About DAC

The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for electronic design automation (EDA) and silicon solutions. A diverse worldwide community of more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives as well as researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight of DAC is its exhibition and suite area, with approximately 200 of the leading and emerging EDA, silicon, and intellectual property (IP) companies and design services providers. The conference is sponsored by the Association for Computing Machinery (ACM), the Electronic System Design Alliance (ESDA), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM's Special Interest Group on Design.


About Aldec

Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, High-Performance Computing Platforms, Embedded Development Systems, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.

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