Can’t make the webinar? Go ahead and register. You’ll receive a link to view the recording at your convenience. ‘Eliminating Clock Domain Crossing (CDC) Issues Early in the Design Cycle’ In this webinar, we’ll discuss typical synchronizer structures to put in place for CDC crossings as well as the most common mistakes in their structure. We’ll also cover some of the functional problems that often arise due to incorrect synchronization, as well as how to verify a project against CDC issues during the RTL design and RTL simulation design stages. Date: Thursday, August 13, 2015 Register for EU 3:00PM to 4:00PM CEST Date: Thursday, August 13, 2015 Register for US 11:00AM to 12:00PM PDT Presented by Pavel Leshtaiev, Aldec Software Product Manager Pavel is a Product Manager at Aldec for DRC and CDC solutions. He received his MS in Special-Purpose Computer Systems from the Chernihiv State University of Technology, Ukraine. Pavel has been directly with ALINT™ and ALINT-PRO-CDC™ since 2009, with experience in roles such as SQA Engineer, SQA Team Leader, Applications Engineer, Project Manager and Product Manager. He has deep practical experience in design verification techniques and best practices, particularly in the field of FPGA design. Related Press Release: Aldec enhances ALINT-PRO-CDC with Advanced Violation Analysis Capabilities and an Extended Set of Dynamic Checks Download ALINT-PRO-CDC 2015.08 Evaluation License Aldec is a global industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. +1.702.990.4400 sales@aldec.com www.aldec.com Don't want to receive email Updates? Unsubscribe here.
