Can’t make the webinar? Go ahead and register. You’ll receive a link to view the recording at your convenience. ‘Physical Testing for DO-254’ For DAL A/B FPGAs, applicants are recommended to verify the device behavior at the silicon level (physical testing) in order to satisfy the objectives defined in RTCA/DO-254 Section 6.2.1 Verification Process. This is recommended because there are significant errors that may potentially impact safety but can only be found through physical testing. However, physical testing of the FPGA in the target board is quite challenging and not feasible in most cases. That is why both FAA and EASA allow for alternate verification means if physical tests in the target board are not feasible. Learn in this webinar a methodology that enables requirements-based physical testing with 100% FPGA I/O controllability and visibility necessary to satisfy the objectives. Agenda DO-254 Verification Process Physical testing in DO-254 Simulation vs. Test Example of errors that can be found through physical tests, but not in simulation Aldec’s solution as an alternate verification mean (allowed by FAA/EASA) DO-254/CTS™ Overview (place in DO-254 Flow, Benefits, Demo) Q & A Date: Thursday, August 6, 2015 Register for EU 3:00PM to 4:00PM CEST Date: Thursday, August 6, 2015 Register for US 11:00AM to 12:00PM PDT Presented by with Aldec DO-254 Program Manager, Louie De Luna Louie is responsible for FPGA level in-target testing technology and requirements lifecycle management for DO-254 and other safety-critical industry standards. He received his B.S. in Computer Engineering from University of Nevada in 2001. His practical engineering experience includes areas in Acceleration, Emulation, Co-Verification and Prototyping, and he has held a wide range of engineering positions that include FPGA Design Engineer, Applications Engineer, Product Manager and Project Manager. Aldec is a global industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. +1.702.990.4400 sales@aldec.com www.aldec.com Don't want to receive email Updates? Unsubscribe here.
