FPGAs for Verification, UVM Simulation Acceleration with Scalable FPGA Platforms Presented by Alex Grove, FirstEDA Applications Specialist Most ASIC IP and SoC platforms will be validated at some point using FPGAs; this task is typically referred to as ASIC FPGA prototyping. At the same time, FPGAs are increasingly being used for verification due to the performance and scalability of these systems. In this webinar, we will introduce an approach where UVM tests can be accelerated with the use of an FPGA co-emulator. The approach is built upon industry standards SystemVerilog and SCE-MI, and requires no changes to the test environment to accelerate. This enables tests to be moved seamlessly from simulation to the accelerator and back again. Date: Thursday, July 9, 2015 Register for EU 3:00PM to 4:00PM CEST Date: Thursday, July 9, 2015 Register for US 11:00AM to 12:00PM PDT UVM: What’s Stopping You? Easier UVM and FPGA-based acceleration work together to increase UVM productivity By Doug Amos, One-Man-Army FPGA Consultant These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based UVM. Many verification teams have ramped up on UVM, but others have yet to take the plunge. Why is that? And how big a “plunge” is it, anyway? If UVM is as great as all that, then why hasn’t everybody adopted it… [read more] Aldec is a global industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. +1.702.990.4400 sales@aldec.com www.aldec.com Don't want to receive email Updates? Unsubscribe here.
