FPGA Vendor IP, Primitives & Simulation LibrariesCategory : Supported Standards & LibrariesAldec simulators provide comprehensive support for simulating FPGA designs using vendor-specific IP, primitives, macros, and simulation libraries. Designers can verify vendor IP and device-specific components directly in the simulation environment. Aldec simulators support FPGA IP and simulation libraries from leading vendors, including AMD, Altera, Lattice Semiconductor, and Microchip. Support includes VHDL, Verilog, SystemVerilog, and mixed-language designs, depending on the vendor IP, libraries, and simulator language license. An extensive set of pre-compiled FPGA vendor simulation libraries is updated with each release to support the latest FPGA development tools, devices, and IP. This eliminates the need to manually compile commonly used libraries and simplifies simulator setup. Pre-compiled libraries are available for download from the Aldec website, and users can also compile additional or custom vendor libraries as needed. Aldec simulators support RTL, IP-level, mixed-language, and post-implementation simulation of designs containing vendor IP, primitives, macros, memory models, clocking resources, transceivers, and other device-specific components.
