The avionics industry’s growing need for TLM

Avionics systems increasingly leverage FPGAs [field-programmable gate arrays] and SoC [system-on-chip] FPGAs with high-speed interfaces such as PCIe and Ethernet to deliver greater performance and reliable connectivity for military and civil aviation. However, if the underlying FPGA design needs to demonstrate development assurance based on DO-254/ED-80 (documents providing guidance for the development of airborne electronic hardware), verification becomes very challenging. In these cases, transaction-level modeling (TLM) may be the answer.

Henderson, NV, USA – May 18, 2023 – The ubiquity and standardization of PCIe, Ethernet, and other serial high-speed interfaces – plus their availability within FPGAs [field-programmable gate arrays] and SoC [system-on-chip] and FPGAs as embedded hard IP – made them very popular in military avionics and aerospace, and for their use in supporting safety-critical functionality. In addition, FPGA vendors provided some great development tools for device configuration and integration.

All are of considerable benefit to design engineers. However, the increasing use of multiple high-speed serial interfaces in safety-critical applications comes at a price. For certification purposes it must be proved that the devices function as intended and with high reliability. Unfortunately, that is difficult to do for three reasons:

• Physical (in-hardware) test of the FPGA with the high-speed interfaces in the target circuit board can produce nondeterministic responses.
• There is a lack of FPGA input controllability and output visibility.
• The avionics industry struggles to adopt the appropriate verification techniques and methodologies as quickly as the commercial sector, for example, which can lead to significant project delays and costs.

TLM combined with a suitable test platform solves all three problems. For further information, please visit our article in Military Embedded Systems.